Frequency Scaled Segmented Scan Chain for IC Testing
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Solution Overview
Problem
Conventional scan architectures in integrated circuits consume excessive power during testing, limiting the frequency and duration of self-tests and increasing manufacturing costs due to high power dissipation, which restricts the number of circuits that can be tested simultaneously.
Innovation Solution
The implementation of a frequency-scaled segmented (FSS) scan method, where the scan chain is divided into segments clocked by out-of-phase clocks, allowing the scan frequency to be scaled up while maintaining the internal design frequency constant, thereby reducing power consumption and enabling more efficient testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan frequency is increased to reduce test time, then productivity improves, but power consumption increases
Solution Approach 1:
The scan chain is divided into multiple segments (first segment, second segment, third segment) that can be operated independently or in parallel. This segmentation allows the test system to distribute the scanning workload across multiple segments clocked by out-of-phase clocks, enabling higher overall throughput while controlling power consumption by activating only necessary segments at any given time.
Solution Approach 2:
The patent employs out-of-phase clocks to periodically activate different segments of the scan chain. By using periodic clocking with different phases, the system can maintain high average throughput while ensuring that not all segments are active simultaneously, thereby reducing peak power consumption and enabling sustained high-speed operation.
2Productivity
If multiple circuits are tested in parallel to improve productivity, then output increases, but power dissipation increases
Solution Approach 1:
The scan architecture is segmented into multiple independently controllable segments that can be allocated to different circuits under test. This allows the system to dynamically assign segments to multiple circuits in parallel while controlling total power consumption by managing which segments are active for each circuit, thereby enabling scalable parallel testing without linear power increase.
3Measurement precision
If scan chain length is increased to test more logic, then measurement precision improves, but power consumption increases
Solution Approach 1:
The scan chain is divided into multiple segments that can be configured to cover different portions of the logic under test. This segmentation allows comprehensive test coverage to be achieved by distributing test patterns across segments rather than requiring a single long continuously-active scan chain, thereby maintaining measurement precision while reducing power consumption through selective segment activation.
Data Source
AI summary
A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.