Frequency Sensor Detecting Side-Channel Attacks

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Solution Overview

Problem

Cryptographic systems face challenges in detecting side-channel attacks, particularly when attackers modify clock frequencies to gain sensitive information, leading to false negatives and positives in existing frequency sensors.

Innovation Solution

A frequency sensor apparatus and method that compares clock signal periods to delay periods, using flip-flops and delay elements to output signals indicating whether the clock frequency is within or outside a specified range, with feedback mechanisms to avoid false negatives and positives.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing frequency sensors are used to detect clock frequency changes in cryptographic systems, then the system can identify some side-channel attacks, but the sensors produce false negatives and false positives that reduce detection reliability

Engineering Contradiction:
Improvedetection reliabilityVSAvoidfrequency measurement accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The frequency sensor is divided into multiple independent components: a delay element with programmable delay time, a launch flip-flop, a capture flip-flop, and an output stage. Each component performs a specific function in the frequency detection process, allowing for modular optimization and reduced interference between functions, thereby improving both reliability and measurement precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sensor uses feedback mechanisms where the output signals from the capture flip-flop are fed back to control the delay element programming. This feedback loop allows the system to automatically adjust the delay time based on detected frequency conditions, enabling the sensor to adapt to different attack scenarios and reduce false positives while maintaining high detection reliability.

Inventive Principle:
Principle #23Feedback

2Adaptability or versatility

If the delay time in the frequency sensor is fixed, then the circuit design is simpler, but the sensor cannot adapt to different clock frequency ranges and attack scenarios

Engineering Contradiction:
Improvefrequency range adaptabilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The delay element is designed with dynamic programmability, allowing the delay time to be changed during operation based on the detected clock frequency and attack type. This dynamic adjustment capability enables the sensor to adapt to different frequency ranges without requiring multiple fixed circuits, achieving versatility while maintaining relatively simple circuit architecture through controlled reconfigurability.

Inventive Principle:
Principle #15Dynamics

3Speed

If the frequency sensor operates at high speed to detect rapid frequency changes, then detection responsiveness is improved, but the sensor becomes more susceptible to timing errors and false detections

Engineering Contradiction:
Improvedetection speedVSAvoidtiming accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The launch flip-flop is triggered in advance of the capture phase, preparing the signal path and ensuring that the delay element is properly configured before the actual frequency measurement begins. This preliminary action allows the system to operate at high speeds while maintaining timing accuracy, as the critical measurement window is optimized and pre-conditioned signals are ready for immediate capture.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9645602B2Frequency sensor for side-channel attack
Publication Date: 2017.05.09 QUALCOMM INC
  • US9645602B2 patent drawing
  • US9645602B2 patent drawing
  • US9645602B2 patent drawing

AI summary

A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus may be used for detecting an incorrect clock frequency. In one example, the apparatus includes a first circuit configured to compare a clock signal period to a delay period. Additionally, in one example, the apparatus includes a second circuit configured to output a first signal. The period of the first signal may be double the clock signal period when the clock signal period is greater than the delay period. The apparatus may, in one example, also include a third circuit configured to output a second signal. The period of the second signal may be greater than double the clock signal period when the clock signal period is greater than the delay period.