Frequency Synthesizer Dynamic Calibration for Low-Power RTC Clocks
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Solution Overview
Problem
Conventional phase-locked loop (PLL)-based frequency synthesizers used in electronic devices are inefficient, leading to reduced battery life and increased space usage, particularly in generating low-frequency clock signals for real-time clock applications from high-frequency communications circuitry.
Innovation Solution
An adjustable oscillator circuit and calibration circuit that dynamically adjust the frequency of the output signal by comparing transitions of a frequency reference signal to a reference value, enabling and disabling the frequency reference generator circuit based on the determined difference, allowing for efficient generation of low-frequency clock signals while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a phase-locked loop (PLL) is used to generate low-frequency clock signals from high-frequency clock signals, then low-frequency clock signals can be generated, but power consumption increases and battery life decreases
Solution Approach 1:
The patent implements dynamic calibration intervals where the frequency reference generator circuit is enabled periodically rather than continuously. The calibration circuit determines relationships between clock signals at different frequencies and disables the reference generator between calibration periods, creating periodic action that reduces power consumption while maintaining accuracy.
Solution Approach 2:
The patent applies dynamic adjustment by modifying the operational state of the frequency reference generator circuit based on calibration needs. The system transitions between enabled and disabled states dynamically, adjusting the calibration interval based on determined relationships between clock signals, thereby optimizing power consumption while maintaining functionality.
2Measurement precision
If separate crystal oscillators are used for communications and real-time clock functions, then accurate clock signals can be generated for both functions, but device space increases and cost increases
Solution Approach 1:
The patent makes a single frequency reference generator circuit serve multiple functions by using it to calibrate both communications circuitry and real-time clock functions. The calibration circuit enables this one reference source to support multiple clock generation needs, eliminating the requirement for separate crystal oscillators while preserving accuracy for both applications.
Solution Approach 2:
The patent combines the functions of multiple separate oscillators into a unified system. By merging the real-time clock function and communications clock function under a single frequency reference generator with dynamic calibration, the system reduces component count and device space while maintaining the precision required for both functions.
3Productivity
If conventional PLL-based approaches are used to generate low-frequency clock signals, then clock signals can be generated, but circuitry efficiency decreases and battery life is reduced
Solution Approach 1:
The patent improves circuitry efficiency by implementing periodic calibration instead of continuous operation. The frequency reference generator circuit is enabled only during calibration intervals and disabled otherwise, creating periodic action that reduces power consumption and extends battery life while maintaining the ability to generate accurate low-frequency clock signals when needed.
Solution Approach 2:
The patent changes the operational parameters of the frequency reference generator circuit by adjusting calibration intervals dynamically. Based on determined relationships between clock signals, the system modifies when the reference generator is enabled or disabled, optimizing the balance between accuracy maintenance and power consumption reduction.
Data Source
AI summary
An apparatus includes an adjustable oscillator circuit configured to generate an output signal having a frequency that varies responsive to a frequency control signal and a frequency reference generator circuit configured to produce a frequency reference signal. The apparatus further includes a calibration circuit configured to determine a relationship of the output signal to the frequency reference signal and to enable and disable the frequency reference generator circuit based on the determined relationship.