Frequency Synthesizer Locking With Simultaneous Value Loading

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Solution Overview

Problem

Conventional digital control loop architectures in frequency synthesizers lack dynamic frequency transition capabilities, requiring reconfiguration and initial locking procedures, which hinders rapid frequency changes and flexibility in clock signal generation, especially in programmable logic devices.

Innovation Solution

A method and circuit for generating frequency synthesizer outputs that allow simultaneous loading of new frequency values while locking to a new frequency, with adaptive digital loop bandwidth adjustment using error signals to optimize frequency transitions and minimize overshoot.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional digital control loop architectures are used for frequency synthesis, then the system structure is simple and stable, but dynamic frequency transitions require reconfiguration and initial locking procedures which slow down frequency changes

Engineering Contradiction:

Improvefrequency transition speedVSAvoidcontrol loop architecture complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent implements a dual-mode control loop architecture that dynamically switches between low-frequency mode (for fast acquisition) and high-frequency mode (for precise locking). This dynamic reconfiguration of the control loop bandwidth allows the system to achieve rapid frequency transitions while maintaining stable locking, resolving the contradiction between transition speed and system stability without requiring full reconfiguration.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system performs preliminary frequency acquisition using the low-frequency mode before transitioning to high-frequency mode for final locking. This preliminary action allows the frequency synthesizer to quickly approach the target frequency and reduce the locking time, thereby improving frequency transition speed without compromising the stability of the final locked state.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If simultaneous loading of new frequency values is implemented during locking, then frequency transition flexibility improves, but risk of overshoot and locking failures increases

Engineering Contradiction:

Improvefrequency transition flexibilityVSAvoidlocking reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent employs feedback control mechanisms that continuously monitor the frequency synthesis process and adjust the control loop bandwidth accordingly. When new frequency values are loaded during locking, the feedback system detects the change and dynamically adapts the loop parameters to prevent overshoot and ensure successful locking, thereby maintaining reliability while enabling flexible simultaneous frequency updates.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system prepares for potential frequency updates by implementing cushioning mechanisms that prevent overshoot. Before allowing simultaneous loading of new frequency values, the system establishes protective control measures that limit the rate of frequency change and provide damping, thus preventing locking failures while maintaining the flexibility to update frequencies during operation.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Productivity

If adaptive digital loop bandwidth adjustment is used, then frequency transition optimization improves, but control logic complexity increases

Engineering Contradiction:

Improvefrequency synthesis efficiencyVSAvoidcontrol logic complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the frequency synthesis process into distinct phases (acquisition phase and locking phase) with corresponding low-frequency and high-frequency modes. This segmentation allows the control logic to selectively apply different bandwidth settings for different phases, optimizing frequency transitions without requiring continuously complex adaptive control, thus improving productivity while keeping control logic manageable.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system optimizes frequency transitions by changing the loop bandwidth parameter based on the synthesis phase. During acquisition, a low-frequency mode with wider bandwidth is used for fast response; during locking, a high-frequency mode with narrower bandwidth is used for precision. This parameter change approach improves synthesis efficiency while avoiding the need for continuously complex adaptive logic.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7576622B1Method of generating an output of a frequency synthesizer

Publication Date: 2009.08.18 XILINX INC

AI summary

A method of generating an output of a frequency synthesizer is disclosed. The method comprises the steps of generating an output of the frequency synthesizer based upon frequency synthesizer values and a reference clock signal; receiving a command comprising a first new frequency synthesizer value; locking to a new frequency based upon the first new frequency synthesizer value; and simultaneously loading a second new frequency synthesizer value while locking to the new frequency. A circuit for generating an output of a frequency synthesizer is also disclosed.