Frequency Synthesizer PLL Architecture for Low Phase Noise
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Solution Overview
Problem
Frequency synthesizers in signal generation equipment suffer from high phase noise and limited step size, which restricts the accuracy and sensitivity of testing systems, particularly due to the presence of dividers in the feedback path.
Innovation Solution
The implementation of frequency converters, such as mixers, in place of dividers in the feedback path, along with the use of phase-locked loops, yttrium-iron-garnet (YIG) oscillators, and variable-multiplier circuits to reduce phase noise and achieve smaller step sizes, allowing for fine resolution and wide frequency tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dividers are used in the feedback path of a frequency synthesizer, then the circuit structure is simpler, but the phase noise increases and step size becomes larger
Solution Approach 1:
The patent removes the divider from the feedback path of the phase-locked loop, extracting the frequency division function out of the critical signal path. Instead, a mixer multiplies the VCO output by a divided version of the reference signal, achieving frequency synthesis without placing a divider in the feedback path, thereby reducing phase noise while maintaining structural feasibility
Solution Approach 2:
The patent replaces the mechanical/divider-based frequency division approach with an electronic multiplication approach using a mixer. The mixer multiplies the VCO output signal by a frequency-divided reference signal, effectively substituting the divider's function with a multiplication operation that does not degrade phase noise in the feedback path
2Device complexity
If dividers are used in the feedback path, then the device complexity is reduced, but the frequency tuning resolution becomes coarser
Solution Approach 1:
The divider is extracted from the feedback path, allowing the frequency synthesis to achieve fine resolution through the multiplication operation. The reference signal is divided by a large integer N outside the feedback path, and the mixer's multiplication provides the necessary frequency multiplication with fine resolution capability
Solution Approach 2:
The patent changes the operational parameters by using frequency multiplication instead of division in the feedback path. The mixer multiplies frequencies rather than dividing them, enabling fine frequency resolution through the relationship Fout = (N/K) * Fref, where both N and K can be independently controlled to achieve precise frequency steps
3Device complexity
If a single phase-locked loop is used, then the device complexity is lower, but it cannot simultaneously achieve fast acquisition and low phase noise
Solution Approach 1:
The patent divides the frequency synthesis function into two separate phase-locked loops: a first PLL for fast frequency acquisition and a second PLL for low phase noise operation. This segmentation allows each loop to be optimized for its specific function, with the system switching between them based on operational requirements
Solution Approach 2:
The patent implements a dynamic system where the output signal source is switched between two different PLL configurations. The first PLL operates during acquisition with coarser resolution but faster response, while the second PLL operates during normal operation with fine resolution and low phase noise, allowing the system to adapt to different operational states
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces phase noise and enables smaller step sizes, enhancing the accuracy and sensitivity of frequency synthesizers, thereby improving the performance of signal generation equipment.
Implementation Method 1
In each element, a mixer can multiply an input signal by a frequency-divided version of the input signal
Implementation Method 2
An output signal provided by a voltage-controlled oscillator varies throughout a much wider range
Implementation Method 3
A first phase-locked loop having a fast acquisition time can be provided. A second phase-locked loop having low phase noise can be provided in parallel with the first phase-locked loop
Implementation Method 4
These frequency synthesizers can provide low phase noise by employing a yttrium-iron-garnet (YIG) oscillator. A YIG oscillator can provide a low phase noise oscillator output signal that is highly frequency stable
Implementation Method 5
When the YIG oscillator is correctly tuned, the second phase-locked loop can be switched in to replace the first phase-locked loop
Data Source
AI summary
Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.