Frequency Synthesizer Sleep Control With Phase-Coherent Wake-Up

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Solution Overview

Problem

Wireless communication devices face high power consumption issues due to the continuous operation of frequency synthesizer circuits, even during idle periods, which affects battery life without effectively managing power-down states without compromising phase coherency.

Innovation Solution

A frequency-generating circuit with a controller that generates a power-down control signal to shut down parts of the frequency synthesizer circuit during sleep periods, while maintaining the accumulated value of the accumulator to ensure phase coherency upon wake-up, using a method that estimates the future accumulated value based on the reference clock cycle and sleep period length.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the frequency synthesizer circuit operates continuously to maintain phase coherency, then phase coherency is preserved, but power consumption increases

Engineering Contradiction:
Improvephase coherencyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The controller calculates and stores the future accumulated value before the accumulator is reset, so that when the circuit wakes from sleep mode, the accumulated value is already prepared and can be directly loaded without requiring continuous operation of the accumulator

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the operational state of the frequency synthesizer circuit, switching between active and sleep modes based on whether data transmission or reception is occurring, while maintaining phase coherency through calculated accumulated values

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If the frequency synthesizer circuit is powered down during idle periods, then power consumption is reduced, but phase coherency is compromised

Engineering Contradiction:
Improvepower consumptionVSAvoidphase coherency
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The controller performs preliminary calculation of the accumulated value that would have been generated during the sleep period based on the reference clock signal characteristics and sleep duration, then loads this pre-calculated value after wake-up, eliminating the need for continuous accumulator operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The controller acts as an intermediary that bridges the gap between the accumulator's operational state and the required phase information, by calculating and providing the appropriate accumulated value to maintain phase coherency without requiring the accumulator to remain active

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3340469B1Methods for controlling a frequency synthesizer circuit and a frequency-generating circuit utilizing the same
Publication Date: 2019.10.23 MEDIATEK INC
  • EP3340469B1 patent drawingFigure 1
  • EP3340469B1 patent drawingFigure 2
  • EP3340469B1 patent drawingFigure 3

AI summary

A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.