Frequency Synthesizer Phase Interpolation for Zero Deterministic Jitter
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Solution Overview
Problem
Existing clock signal generation methods in digital systems often result in deterministic jitter, which compromises signal quality and can lead to system malfunction, especially in high-performance applications, due to limitations in power consumption and IC area.
Innovation Solution
A frequency synthesizer system generates two intermediate clock signals with the same frequency but different cycle patterns, controlled by step-size control logic, which are then phase interpolated to produce an output clock signal with zero deterministic jitter by averaging their frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digital frequency synthesizer uses time averaging to achieve accurate frequency, then frequency accuracy is improved, but deterministic jitter is generated due to minimum step-size limitations
Solution Approach 1:
The patent divides the frequency synthesis process into multiple parallel channels, each generating clock signals with different deterministic jitter patterns. By segmenting the overall frequency synthesis function across multiple synthesizers with offset deterministic jitter, the system achieves fine frequency resolution without the deterministic jitter limitations of a single synthesizer.
2Reliability
If an analog fractional N frequency synthesizer is used to minimize deterministic jitter, then deterministic jitter is reduced, but power consumption and IC area increase
Solution Approach 1:
The patent combines multiple digital frequency synthesizers in parallel, each operating at the same frequency but with offset deterministic jitter patterns. By merging the outputs of these synthesizers through phase interpolation, the system achieves deterministic jitter reduction equivalent to analog solutions while maintaining the power and area advantages of digital implementation.
3Reliability
If the minimum step-size is reduced to minimize deterministic jitter, then deterministic jitter is improved, but power consumption and IC area increase
Solution Approach 1:
Instead of reducing step-size within a single frequency synthesizer (one-dimensional approach), the patent introduces a new dimension by using multiple parallel synthesizers with offset deterministic jitter patterns. This multi-dimensional approach achieves fine frequency resolution and deterministic jitter reduction without requiring smaller step-sizes or increased IC area in individual synthesizers.
Data Source
AI summary
A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (fN), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (fA). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by fN and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with fA/N, and is free of deterministic jitter.