Fringe Capacitance Calculation for MOSFET Layout Simulation
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Solution Overview
Problem
Circuit simulation for semiconductor devices faces inaccuracies due to errors in capacitance simulation near MOS-FET transistors, particularly in gate fringe, overlap, and contact plug capacitances, leading to significant simulation errors in frequency characteristics, especially with miniaturization.
Innovation Solution
A circuit simulation device with a measurement unit to determine specific spaces between contacts and a calculation unit to accurately calculate fringe capacitance between the gate and diffusion layers, allowing for precise simulation by considering varying capacitance components based on contact plug arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed value is used for gate fringe capacitance, then the device complexity is reduced, but the simulation accuracy deteriorates
Solution Approach 1:
The patent changes the parameter of gate fringe capacitance from a fixed value to a variable value that depends on the number of contact plugs. The capacitance is calculated as C_fringe = C0 + k × N, where N is the number of contact plugs, thereby adapting the capacitance parameter to the actual device structure and improving simulation accuracy
Solution Approach 2:
The patent performs preliminary extraction of capacitance values based on layout design data before circuit simulation. By pre-calculating the gate fringe capacitance considering the contact plug arrangement, the system prepares accurate capacitance parameters in advance, avoiding the need for complex real-time calculations during simulation
2Device complexity
If the capacitance near MOS-FET transistor is neglected, then the calculation complexity is reduced, but the simulation accuracy deteriorates
Solution Approach 1:
The patent extracts and separately calculates the capacitance near the MOS-FET transistor, specifically the gate fringe capacitance and gate overlap capacitance. By isolating these capacitance components and calculating them independently based on layout data, the system includes their effects in the simulation without significantly increasing overall calculation complexity
Solution Approach 2:
The patent segments the total capacitance into distinct components: gate fringe capacitance, gate overlap capacitance, and other capacitances. Each component is calculated separately using specific formulas and layout parameters, allowing for more accurate and manageable computation of the total capacitance effect
3Productivity
If miniaturization is advanced to increase device density, then the productivity is improved, but the simulation accuracy deteriorates
Solution Approach 1:
The patent applies local quality by considering the specific arrangement of contact plugs in the layout design. The gate fringe capacitance calculation takes into account the local configuration of contact plugs near the gate, which becomes increasingly important as device dimensions are reduced. This localized consideration ensures accurate simulation even in miniaturized devices
Data Source
AI summary
A circuit simulation device includes a measurement unit, a calculation unit, and a processing unit. The measurement unit measures first spaces between adjacent contacts of a plurality of first contacts provided on a source diffusion layer in a line in a direction along which a gate electrode of a transistor extends and also a space between adjacent contacts of a plurality of second contacts provided on a drain diffusion layer in a line in the direction, based on layout design data, and second spaces between the first contacts and the gate electrode and spaces between the second contacts and the gate electrode. The calculation unit calculates a fringe capacitance between the gate electrode, the source diffusion layer, and the drain diffusion layer of the transistor, based on the first and second spaces. The processing unit executes layout simulation based on the fringe capacitance of the transistor.