Fringeless Transistor Gate Structures for Multi-Voltage Circuit Density

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Solution Overview

Problem

The challenge in semiconductor technology is to design field effect transistors that operate at different operating voltages while maintaining high device density, which is difficult to achieve with existing peripheral circuitry.

Innovation Solution

The semiconductor structure comprises multiple field effect transistors with specific gate electrode configurations and trench isolation structures, including a first field effect transistor with a semiconductor gate electrode portion and a second field effect transistor with a stack of semiconductor gate electrode portions, along with dielectric material layers, to enable efficient operation at various voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If field effect transistors are configured to operate at different operating voltages, then operational versatility is improved, but device density deteriorates

Engineering Contradiction:
Improveoperating voltage rangeVSAvoiddevice density
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by configuring different gate electrode structures in different regions of the semiconductor device. Specifically, fringeless transistors use gate electrodes with different geometries (e.g., merged gate structures) compared to conventional transistors, allowing each region to be optimized for its specific voltage requirement while maintaining high overall device density through localized structural variations rather than uniform design

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If fringeless transistor configurations are used, then device density is improved, but manufacturing complexity worsens

Engineering Contradiction:
Improvedevice densityVSAvoidgate electrode structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges adjacent gate electrode portions to form continuous gate structures for fringeless transistors. By combining multiple gate segments into unified structures, the design achieves higher device density while the merging process itself can be integrated into existing semiconductor manufacturing flows, balancing the increased structural complexity with process compatibility

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If multiple gate electrode portions are stacked, then operational voltage control is improved, but manufacturing precision requirements worsen

Engineering Contradiction:
Improvevoltage controlVSAvoidgate electrode alignment
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent employs preliminary patterning actions where gate electrode portions are formed in sequential steps with predetermined geometries. By pre-defining the shapes and positions of individual gate portions before final assembly, the manufacturing process achieves the required precision for stacked configurations while maintaining flexibility in voltage control through the staged formation approach

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240072042A1Transistor circuits including fringeless transistors and method of making the same
Publication Date: 2024.02.29 SANDISK TECHNOLOGIES LLC
  • US20240072042A1 patent drawing
  • US20240072042A1 patent drawing
  • US20240072042A1 patent drawing

AI summary

A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.