Free-Running Oscillator Clocking for PVT-Resilient Multi-Core Domains
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Solution Overview
Problem
Integrated circuit (IC) design faces challenges in managing Process, Voltage, and Temperature (PVT) variations, leading to inefficiencies in clocking digital systems, particularly as technology scales to smaller geometries and the number of processor cores increases, resulting in significant margins that waste available time and complicate synchronous operation.
Innovation Solution
Implementing free running oscillators (FROs) that adapt to PVT variations by synchronizing clock signals across a chip or core domain, using ring oscillators or other implementations, ensuring the clock signal runs at the lowest frequency determined by the worst PVT region, thereby reducing unnecessary margins and enabling flexible, synchronous/asynchronous clocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a central clock is used to synchronize operations across the chip, then synchronous operation is achieved, but excessive margins are required to account for PVT variations, wasting available time
Solution Approach 1:
The patent divides the chip into multiple clock domains, each with its own free-running oscillator. This segmentation allows each domain to operate independently with its own timing, eliminating the need for excessive global synchronization margins while maintaining local synchronous operation within each domain.
Solution Approach 2:
Each clock domain is configured with local free-running oscillators that adapt to the specific PVT conditions of their region. This local adaptation allows each domain to operate at optimal frequency without being constrained by worst-case margins required for global synchronization.
2Speed
If the chip is designed to operate at high frequency (10 GHz) under nominal conditions, then performance is improved, but the chip must account for worst-case PVT conditions, reducing guaranteed operating frequency to 5 GHz
Solution Approach 1:
The free-running oscillators dynamically adapt their frequency to local PVT conditions in each clock domain. This dynamic adaptation allows the system to maintain reliable operation across varying conditions without requiring a static design based on worst-case scenarios, effectively resolving the contradiction between speed and reliability.
3Productivity
If technology scales to smaller geometries and more processor cores are added, then productivity is improved, but the number of synchronous clock domains increases, requiring even larger margins
Solution Approach 1:
By segmenting the chip into multiple independent clock domains with free-running oscillators, the patent enables scaling to more processor cores without proportionally increasing synchronization margins. Each domain operates semi-independently, reducing the global timing constraints that would otherwise limit scalability.
4Reliability
If excessive margins are used to ensure operation under worst-case conditions, then reliability is improved, but operational efficiency decreases due to time wastage
Solution Approach 1:
The patent changes the fundamental parameter of clock synchronization from a single global clock to multiple free-running oscillators with locally adapted frequencies. This parameter change allows the system to maintain reliability under PVT variations while eliminating the excessive time margins required by traditional synchronous designs, thereby improving operational efficiency.
Data Source
AI summary
A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.