Front and Back Redistribution Layout for Compact Semiconductor Packaging
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Solution Overview
Problem
Conventional semiconductor packages face issues of high cost, decreased reliability, and large package sizes, which are not adequately addressed by existing manufacturing methods.
Innovation Solution
The development of a semiconductor device structure and method that incorporates a thin fine-pitch redistribution structure, involving the preparation of logic wafers and redistribution structure wafers with conductive interconnection structures, attachment of semiconductor die, underfilling, molding, and subsequent processing steps to reduce costs and enhance reliability and manufacturability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages are used, then manufacturing cost is high, but reliability is decreased and package size is large
Solution Approach 1:
The patent divides the semiconductor package into separate functional components: a semiconductor die with active circuitry and a separate redistribution structure with conductive traces. This segmentation allows each component to be optimized independently - the die for reliability and the redistribution structure for cost-effective manufacturing and routing flexibility.
Solution Approach 2:
The redistribution structure serves as an intermediary component between the semiconductor die and external connections. It mediates the electrical connections by providing a flexible routing layer that can adapt to different package layouts without requiring complex modifications to the die itself, thereby improving reliability while maintaining manufacturing simplicity.
2Area of stationary object
If conventional redistribution structures are used, then package size is large, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar redistribution routing to three-dimensional vertical routing through redistribution vias. Conductive traces are arranged in multiple layers stacked vertically, allowing electrical connections to be routed in the vertical dimension rather than requiring large horizontal spacing, thus reducing package area while maintaining manageable manufacturing complexity through standardized via formation processes.
Solution Approach 2:
The redistribution structure employs nested conductive traces arranged in multiple concentric or stacked layers. Inner layers provide primary signal routing while outer layers provide shielding or additional routing, allowing compact integration of multiple functions within a small footprint without significantly increasing manufacturing complexity.
Data Source
AI summary
A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.