Front End Precharge for Digital Memory Bit Lines
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Solution Overview
Problem
Current digital memory architectures consume excessive power due to the need to precharge all bit lines before each access cycle, which increases latency and power consumption, especially in multibank memories where only a subset of bit lines are accessed, and do not allow for efficient random row access.
Innovation Solution
The solution involves selectively precharging only the subset of bit lines required for an access operation, allowing the precharge and access cycles to occur simultaneously, and enabling only necessary sense amplifiers to conserve power and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bit lines are precharged before each access cycle, then memory access reliability is ensured, but power consumption increases and latency increases
Solution Approach 1:
The memory bank is divided into multiple sub-banks, and bit lines are segmented into subsets corresponding to each sub-bank. Only the bit lines in the accessed sub-bank are precharged, rather than all bit lines in the entire bank. This segmentation allows selective precharging, reducing power consumption while ensuring reliable access to the required data.
Solution Approach 2:
The precharge operation is applied locally only to the specific subset of bit lines that will be accessed, rather than uniformly to all bit lines. This local precharging approach maintains the necessary voltage levels for reliable access in the active region while avoiding unnecessary power consumption in inactive regions.
2Reliability
If all bit lines are precharged before each access cycle, then memory access reliability is ensured, but access latency increases
Solution Approach 1:
By segmenting the memory bank into sub-banks and corresponding bit line subsets, the precharge operation is confined to only the necessary portion of the memory structure. This reduces the time required for precharge, thereby decreasing access latency while still ensuring reliable access to the targeted data.
Solution Approach 2:
The precharge operation is performed in advance, but only on the specific bit lines that will be accessed. This preliminary action on a reduced set of bit lines allows the memory system to be ready for access faster than if all bit lines were precharged, thus reducing latency.
3Use of energy by moving object
If a subset of bit lines is selectively precharged, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The memory bank is organized into multiple sub-banks with associated bit line subsets. This segmentation enables selective precharging control through sub-bank select signals, allowing the system to power down or skip precharging inactive sub-banks. The added complexity is managed through systematic organization that simplifies control logic.
Solution Approach 2:
The memory system dynamically adjusts the precharge operation based on the access pattern. The sub-bank select signals enable or disable precharging for specific bit line subsets on a per-access basis, creating a dynamic power management system that adapts to actual access requirements rather than using a static all-or-nothing approach.
4Productivity
If all banks are made accessible for simultaneous operations, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The memory system is divided into multiple independent banks that can operate simultaneously. Each bank can be independently activated based on access requirements, allowing the system to provide high bandwidth when multiple banks are accessed while consuming power only for the actively used banks, not all banks.
Solution Approach 2:
Each memory bank is designed with universal functionality to handle read, write, and precharge operations independently. This multi-functionality allows any bank to be activated for simultaneous operations when needed for high bandwidth, while inactive banks remain in a low-power state, optimizing the trade-off between bandwidth and power consumption.
Data Source
Figure 1(a)~1(h)
Figure 2A~2C
Figure 3
AI summary
Methods, apparatuses and systems (2900) of operating digital memory (2904) where the digital memory device (2904) including a plurality of memory cells (713) receives a command to perform an operation on a set of memory cells (713), where the set of memory cells (713) contains fewer memory cells than the device (2904) as a whole and where the device (2904) performs the operation including selectively precharging on the front end of the operation, in response to the receiv command, only a set of bit lines (709) associated with the set of memory cells (713).