Front-End Processor Emulating Byte Addressability for NVM
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Solution Overview
Problem
Current systems require a two-hop process for data transfer between non-volatile memory (NVM) and graphics processing unit (GPU) memory, involving system memory, which increases traffic and congestion, and existing solutions like NVDIMM do not provide direct access to NVM for GPUs.
Innovation Solution
A method and system that utilize a front-end processor connected to a high-speed serial computer expansion bus to emulate byte addressability for block addressable I/O devices like NVM, allowing PCIe compatible devices like GPUs to directly access data from NVM without going through system memory, using a cache for speed and bandwidth optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a two-hop process is used for data transfer between NVM and GPU memory through system memory, then data transfer can be performed using standard interfaces, but traffic and congestion increase
Solution Approach 1:
The system segments the data transfer path into two modes: standard two-hop transfer for compatibility and direct one-hop transfer for performance. The front-end processor separates byte-addressable operations from block-addressable operations, allowing GPU to choose the optimal path based on access patterns.
Solution Approach 2:
The front-end processor acts as an intermediary between the GPU and NVM, providing byte-addressable emulation for block addressable NVM. It mediates between standard interfaces and direct access paths, enabling both compatibility and performance optimization.
2Ease of operation
If byte addressable access is provided for block addressable NVM, then GPU can directly access NVM, but additional hardware emulation is required
Solution Approach 1:
The front-end processor provides self-service by automatically handling the translation and emulation of byte-addressable requests to block-addressable NVM operations. The cache subsystem also self-manages data storage and retrieval, reducing the need for complex control logic.
Solution Approach 2:
The front-end processor serves multiple functions: it emulates byte-addressable memory for GPU access, manages cache operations, handles protocol translation, and provides both one-hop and two-hop transfer paths. This multi-functionality reduces the need for separate dedicated hardware for each function.
3Speed
If direct access from GPU to NVM is enabled, then bandwidth and latency are improved, but system memory involvement is reduced
Solution Approach 1:
The system dynamically selects between one-hop direct access and two-hop system memory access paths based on the type of operation. Byte-addressable requests use direct GPU-to-NVM access through the front-end processor, while block-addressable requests can utilize system memory when beneficial.
Solution Approach 2:
Different parts of the memory system have specialized functions: the front-end processor handles byte-addressable emulation locally at the GPU interface, the cache provides local high-speed storage near the GPU, and system memory provides global storage. Each component optimizes for its specific function rather than being general-purpose.
Data Source
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AI summary
Described herein is a method and system for accessing a block addressable input/output (I/O) device, such as a non-volatile memory (NVM), as byte addressable memory. A front end processor connected to a Peripheral Component Interconnect Express (PCIe) switch performs as a front end interface to the block addressable I/O device to emulate byte addressability. A PCIe device, such as a graphics processing unit (GPU), can directly access the necessary bytes via the front end processor from the block addressable I/O device. The PCIe compatible devices can access data from the block I/O devices without having to go through system memory and a host processor. In an implementation, a system can include block addressable I/O, byte addressable I/O and hybrids thereof which support direct access to byte addressable memory by the host processor, GPU and any other PCIe compatible device.