Front-Side Die Bonding for High-Density 3DIC Interconnects
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Solution Overview
Problem
The density of interconnections between stacked dies in three-dimensional integrated circuits (3DICs) is limited by the number of through-silicon vias, which also introduces thermal stress due to differences in thermal expansion, limiting the scalability of interconnections as the number of devices increases.
Innovation Solution
Bonding the front side metallization layer of one die to the front side metallization layer of another die, using a hybrid bond that combines dielectric and metal features, allows for a higher density of interconnections independent of the through-silicon via density, enabling increased scalability with the number of devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-silicon vias are used to couple metallization layers between stacked dies, then interconnections between dies are established, but the density of interconnections is limited by the density of through-silicon vias
Solution Approach 1:
The patent transitions from vertical through-silicon via interconnections to horizontal front-side metallization layer bonding, effectively changing the dimensional approach to interconnection. By bonding front surfaces of different dies together, the interconnection density is no longer constrained by the vertical via density but can leverage the two-dimensional metallization layer area, significantly increasing the number of possible interconnections.
Solution Approach 2:
Instead of the conventional back-to-front stacking where the back side of the first die couples to the front side of the second die, this patent inverts the approach by coupling front sides to front sides. This inversion allows direct metallization layer-to-metallization layer bonding, eliminating the need for through-silicon vias and enabling higher interconnection density.
2Quantity of substance
If through-silicon vias are increased to provide more interconnections, then the number of interconnections increases, but thermal stress increases due to differences in thermal expansion
Solution Approach 1:
The patent extracts the interconnection function from the through-silicon via structure and relocates it to the front-side metallization layers. By removing the dependency on through-silicon vias, the source of thermal stress expansion mismatch is eliminated, while preserving and enhancing the interconnection capability through alternative metallization layer bonding.
3Ease of manufacture
If conventional back-to-front die stacking is used, then simple stacking is achieved, but the number of interconnections is limited by via density
Solution Approach 1:
The patent merges the interconnection function with the die bonding process itself. By bonding front-side metallization layers directly during the stacking process, the structural bonding function and the electrical interconnection function are combined into a single operation, eliminating the need for separate via formation and enabling higher interconnection density without complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the number of interconnections between dies, decoupling it from the limitations of through-silicon via density, while reducing thermal stress by allowing more efficient signal transmission and reception, thus enhancing the performance and scalability of 3DICs.
Implementation Method 1
Bonding the front side metallization layer of one die to the front side metallization layer of another die, using a hybrid bond that combines dielectric and metal features
Data Source
AI summary
A semiconductor assembly includes a first die having a front side metallization layer. The semiconductor assembly also includes a second side having a front side metallization layer that is bonded to the front side metallization layer of the first die.