Integrated circuit structure with front-side-guided backside source or drain contact
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Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of integrated circuits to the 10 nanometer node or sub-10 nanometer node range, necessitating new methodologies for multi-gate transistors, particularly in bulk silicon substrates, to optimize performance and reduce complexity.
Innovation Solution
Implementing front-side-guided backside source or drain contacts with backside power delivery, which involves forming pinhole contacts from the backside to connect power wires directly to the transistor, simplifying the process flow and increasing process margin, and enabling direct BS power contact and delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but scalability to 10 nanometer node or sub-10 nanometer node range is limited
Solution Approach 1:
The patent inverts the conventional approach by forming source/drain contacts from the backside of the substrate rather than from the front side. This backside contact formation enables precise alignment with the gate structure and allows for scaled feature dimensions while maintaining manufacturing feasibility through inverted process sequencing.
Solution Approach 2:
The patent transitions from two-dimensional front-side contact formation to three-dimensional backside contact formation. By accessing the substrate from the backside dimension, the invention achieves better alignment control and reduced parasitic effects, enabling scaling to 10nm node or below.
2Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates, then cost and compatibility with existing infrastructure are improved, but performance optimization becomes increasingly difficult as dimensions scale down
Solution Approach 1:
By inverting the contact formation approach to backside contacts, the patent maintains compatibility with bulk silicon substrates while achieving improved device performance. The backside contact geometry enables better electrical contact and reduced parasitic effects without requiring substrate replacement.
3Productivity
If feature dimensions are reduced to increase device density, then capacity is increased, but constraints on semiconductor processes become overwhelming
Solution Approach 1:
The patent utilizes the third dimension (substrate thickness) by forming contacts from the backside. This dimensional approach provides additional degrees of freedom for alignment and contact formation, enabling higher device density at scaled dimensions while managing process constraints through geometric control in the vertical dimension.
4Area of stationary object
If power wires and signal wires are integrated together, then layout space is optimized, but electrical resistance and on-chip IR droop increase
Solution Approach 1:
The patent segments the power delivery path from the signal routing by implementing dedicated backside power contacts. This separation allows power wires to be delivered directly to the transistor active region from the backside, minimizing the length of power interconnects on the front side and reducing on-chip resistance and IR droop effects.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
Integrated circuit structures having front-side-guided backside source or drain contacts are described. An integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, and has a backside contact structure thereon. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, and has a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is in contact with an end of the backside dielectric structure and with an end of the backside contact structure.