Front-Side-Guided Backside Source/Drain Contacts for Sub-10nm Scaling
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Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of integrated circuits to the 10 nanometer node or sub-10 nanometer node range, necessitating new methodologies for multi-gate transistors, particularly in bulk silicon substrates, to optimize performance and integration.
Innovation Solution
Implementing front-side-guided backside source or drain contacts through pinhole formation for direct power delivery from the backside, simplifying the process flow and enhancing process margins, enabling backside contact of source/drain, and reducing power network resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision and scalability to 10nm node or below deteriorates
Solution Approach 1:
The patent applies preliminary action by forming the backside contact opening and depositing conductive material before final front-side processing steps. The backside contact structure is prepared in advance during front-side fabrication, allowing subsequent backside substrate removal and contact formation without requiring complex realignment operations. This staged approach enables precise sub-10nm feature scaling while managing process complexity through systematic sequencing.
2Loss of energy
If front-side-guided backside source or drain contacts are implemented, then power network resistance is reduced, but device complexity increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from conventional front-side-only contacts to three-dimensional backside contacts that extend through the substrate thickness. The backside contact opening penetrates the substrate, and conductive material is deposited from the backside surface, creating vertical current paths that reduce power network resistance. This dimensional extension allows direct backside access to source/drain regions, improving power delivery while the front-side guidance mechanism maintains structural organization.
Solution Approach 2:
The patent uses an intermediary approach by introducing a backside contact opening as a mediator structure that connects front-side gate/control structures to backside power/drain contacts. The opening acts as an intermediary pathway, allowing electrical connections to be established through the substrate thickness. This mediator structure enables the decoupling of power delivery paths from signal routing, reducing power network resistance while managing the added structural complexity through standardized opening formation processes.
3Quantity of substance
If multi-gate transistors are scaled down, then device density is increased, but manufacturing precision constraints become overwhelming
Solution Approach 1:
The patent applies segmentation by dividing the contact formation process into distinct segments: front-side contact opening formation, backside substrate removal, backside contact opening formation, and conductive material deposition. Each segment can be optimized independently for manufacturing precision. The backside contact opening is formed after substrate removal, separating it from front-side lithography constraints. This segmentation allows device density to be increased through multi-gate transistor scaling while managing process constraints through independent optimization of each fabrication stage.
Data Source
AI summary
Integrated circuit structures having front-side-guided backside source or drain contacts are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, and has a backside contact structure thereon. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, and has a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is in contact with an end of the backside dielectric structure and with an end of the backside contact structure.