Front-Side Plug RF HEMT on SiC Substrate
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional RF power HEMTs with through substrate via (TSV) plug connections are costly and not fully compatible with standard CMOS processing, limiting their efficiency and frequency performance, especially when using semi-insulating or high-resistivity substrates.
Innovation Solution
A front-side plug connection method for RF HEMTs is developed, utilizing trench etching, plug filling, ion implantation, and dopant activation on Si or SiC substrates, which are fully compatible with CMOS processing, allowing for efficient electrical connection between the source and back-side metallization, reducing RF substrate losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV plug connection is used with semi-insulating substrates, then source plug connection is achieved, but manufacturing cost increases and CMOS compatibility is reduced
Solution Approach 1:
The patent forms conductive regions and openings during frontend processing before substrate thinning, rather than performing TSV formation after thinning. This preliminary action allows standard CMOS processes to be used, eliminating the need for specialized post-thinning processing while achieving the same source plug connection function.
Solution Approach 2:
Instead of forming openings from the back-side after thinning (conventional TSV approach), the patent forms openings from the front-side during frontend processing. This inversion of the processing sequence enables compatibility with standard CMOS fabrication while achieving equivalent electrical connection.
2Reliability
If deep-RIE or laser drilling is used to form front-side openings, then source plug connection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the source plug connection formation from specialized post-thinning processes and integrates it into standard frontend CMOS processing. By taking out the connection formation step and placing it earlier in the process flow, expensive specialized processes like deep-RIE or laser drilling are eliminated.
Solution Approach 2:
The patent uses standard CMOS processing equipment and techniques (trench etching, plug filling, ion implantation) to achieve source plug connection, making the same manufacturing infrastructure serve multiple functions including both device fabrication and plug connection formation, thereby reducing overall manufacturing cost.
3Loss of energy
If semi-insulating substrates are used, then high frequency losses are minimized, but manufacturing complexity increases
Solution Approach 1:
The patent changes the substrate parameter from requiring semi-insulating to allowing conductive substrates. By modifying the electrical conductivity parameter of the substrate and compensating through frontend-formed conductive regions, the patent simplifies substrate selection while maintaining low high-frequency loss performance through the integrated plug connection design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of RF HEMTs with improved efficiency and frequency performance while being cost-effective and compatible with standard CMOS processing, reducing substrate losses and enhancing device packaging ease.
Implementation Method 1
growing a plurality of high-resistance crystalline silicon epitaxial layers on a crystalline semiconductor substrate
Implementation Method 2
forming a plurality of inactive dopant regions in at least some of the epitaxial layers
Implementation Method 3
An electrically conductive structure is formed from the activated dopant regions. The electrically conductive structure extends in the vertical direction through the epitaxial layers with the activated dopant regions toward the III-nitride compound semiconductor device structure, and is electrically connected to the source
Data Source
AI summary
A compound semiconductor device includes a plurality of high-resistance crystalline silicon epitaxial layers and a plurality of activated dopant regions disposed in a same region of at least some of the epitaxial layers so that the activated dopant regions are aligned in a vertical direction perpendicular to a main surface of the epitaxial layers. The compound semiconductor device further includes an III-nitride compound semiconductor device structure disposed on the main surface of the epitaxial layers. The III-nitride compound semiconductor device structure has a source, a drain and a gate. An electrically conductive structure is formed from the activated dopant regions. The electrically conductive structure extends in the vertical direction through the epitaxial layers with the activated dopant regions toward the III-nitride compound semiconductor device structure, and is electrically connected to the source.