3D Chip Stacking with Front-Side TSVs and Hybrid Bonding
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Solution Overview
Problem
The existing wafer bonding technology for 3D ICs faces challenges in manufacturing through silicon vias (TSVs) due to the need to etch multiple layers, which increases complexity and requires precise depth control, and the use of filling materials leads to stress matching issues and low interconnection density.
Innovation Solution
A chip stacked structure manufacturing method where TSVs are formed from the front side of the chip, reducing the need to etch the substrate and dielectric layer on the backside, and using a hybrid bonding approach with small bonding metal blocks for high-density interconnections, eliminating the need for filling materials and minimizing stress issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSVs are manufactured from the side of the silicon substrate, then electrical connection between TSV and circuit structure is achieved, but etching difficulty increases due to multiple layers requiring etching
Solution Approach 1:
The patent inverts the conventional TSV manufacturing approach by forming TSVs from the front side of the chip (where the functional layer is located) rather than from the back side of the substrate. This reversal changes the etching sequence from etching substrate first then functional layer dielectric to etching functional layer dielectric first then substrate, thereby reducing etching difficulty while maintaining electrical connection reliability
2Reliability
If TSV depth is increased to contact circuit structure, then electrical connection is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary action by forming the TSVs before bonding the chips together. This allows the TSVs to be created with optimized depth and positioning while the chip is still accessible for processing, avoiding the need for precise deep etching through bonded interfaces and reducing manufacturing precision requirements
3Stability of the object's composition
If filling materials are used in bonding, then chip bonding is achieved, but stress matching issues and low interconnection density occur
Solution Approach 1:
The patent extracts and eliminates the filling material from the bonding process. Instead of using filling materials to bond chips together, the invention directly bonds the chips through their respective dielectric layers and bonding metal blocks, thereby avoiding stress matching issues and enabling higher interconnection density without the complexity of filling material integration
Data Source
AI summary
A chip stacked structure includes a first chip and a second chip. The first chip includes a first substrate, a first functional layer, and first through silicon vias. A diameter of the first through silicon via close to the first functional layer is greater than a diameter of the first through silicon via close to the first substrate. The second chip includes a second substrate and a second functional layer. The chip stacked structure further includes a first redistribution layer disposed on a side that is of the second functional layer and that is away from the second substrate, a first dielectric layer disposed between the first substrate and the first redistribution layer, and a plurality of first bonding metal blocks disposed in the first dielectric layer.