3D Frontend Module Layout for High-Speed ATE Signal Integrity
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Solution Overview
Problem
Conventional automatic test equipment (ATE) struggles to accurately measure high-speed semiconductor devices with transmission speeds of 28 Gbps or 40 Gbps due to significant signal loss and waveform distortion in the transmission path between pin electronics ICs and the device under test (DUT).
Innovation Solution
The interface apparatus integrates multiple pin electronics ICs into a frontend module within the interface apparatus, reducing the transmission distance between the ICs and the DUT, using flexible printed circuit (FPC) cables and orthogonal printed circuit boards, and employing a cooling device to minimize signal loss and distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pin electronics ICs are mounted on a PE board housed in the test head, then the device structure is conventional and easy to manufacture, but signal loss and waveform distortion increase at transmission speeds above 20 Gbps
Solution Approach 1:
The patent transitions the PE mounting structure from a conventional 2D board layout to a 3D integrated module architecture. The PE ICs are mounted on multiple PCBs that are stacked and arranged in three-dimensional space, with the socket board positioned at the bottom and PE ICs arranged above it. This dimensional change reduces the transmission distance between PE ICs and the DUT, thereby reducing signal loss and waveform distortion at high speeds.
Solution Approach 2:
The patent implements a nested structure where the PE ICs are integrated within a module that contains multiple PCBs arranged in a hierarchical manner. The socket board forms the base layer, with additional PCBs stacked above it, creating a nested configuration. This nesting reduces the overall transmission path length while maintaining organizational structure, addressing the signal integrity issue at high transmission speeds.
2Adaptability or versatility
If multiple cables are used to connect the socket board to the test head, then the interface apparatus can relay electrical connections, but the transmission path becomes long and causes signal degradation
Solution Approach 1:
The patent merges the socket board and multiple PE ICs into a single integrated module structure. Instead of having separate cables connecting individual components to the test head, the entire assembly (socket board + PE ICs + interconnections) functions as one unified unit. This combining eliminates the need for long external cables, reducing transmission path length while maintaining the electrical connection capability to relay signals between the test head and multiple DUTs.
3Device complexity
If the transmission distance between PE ICs and DUT is long, then the conventional architecture is simpler, but signal loss and waveform distortion increase
Solution Approach 1:
The patent segments the transmission path into two distinct parts: (1) short internal connections within the interface apparatus module, and (2) external connections to the test head. By segmenting the architecture, the patent can optimize the internal segment with a compact 3D layout to minimize transmission distance, while the external segment remains manageable. This segmentation allows the system to achieve both reduced signal loss and acceptable architectural complexity.
Data Source
AI summary
An interface apparatus is provided between a test head and a device under test includes a frontend module configured of multiple pin electronics integrated circuits in the form of a module.