Stacked Transistor Frontside Contacts With Dielectric Cut Separation
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Solution Overview
Problem
The challenge of electrical shorting between upper and lower transistor frontside contacts in stacked transistors due to tight spacing constraints in semiconductor integrated circuits (IC) devices is addressed.
Innovation Solution
The solution involves forming a monolithic frontside contact that is subsequently separated into distinct first and second frontside contacts, with each contact having a conductive portion and a cut sidewall, and incorporating an interlayer dielectric between these sidewalls to maintain electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If tight spacing is used between upper and lower transistor frontside contacts to enable device scaling, then device density and productivity are improved, but the risk of electrical shorting between contacts increases
Solution Approach 1:
The patent divides the contact structure into multiple segments: separate upper and lower frontside contacts, individual cut sidewalls for each contact, and distinct interlayer dielectric regions. This segmentation creates electrical isolation between contacts while maintaining compact spacing, thereby enabling device scaling without increasing shorting risk.
Solution Approach 2:
The interlayer dielectric material serves as an intermediary substance that provides electrical isolation between the upper and lower frontside contacts. By placing this dielectric material in the contact cut region between contacts, the patent achieves reliable electrical separation while maintaining tight spacing for high device density.
2Area of stationary object
If tight spacing is used between upper and lower transistor frontside contacts, then device area is reduced, but manufacturing precision requirements increase to prevent shorting
Solution Approach 1:
The patent performs preliminary formation of cut sidewalls for both upper and lower contacts before final contact separation. This preliminary structuring establishes precise geometric boundaries that guide subsequent processing steps, reducing the precision burden on later alignment-critical steps and enabling tight spacing with controlled manufacturing variability.
Solution Approach 2:
The patent introduces vertical dimensionality through cut sidewalls that extend downward from the contact surfaces. This vertical separation in the depth dimension provides additional isolation between contacts, allowing horizontal spacing to be reduced while maintaining manufacturing feasibility and electrical isolation.
3Reliability
If separate frontside contacts are formed for upper and lower transistors, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
The patent merges the formation processes for upper and lower contacts by simultaneously creating both contact structures and their respective cut sidewalls in an integrated sequence. This combined approach achieves electrical isolation through unified structural design rather than separate independent structures, thereby reducing overall device complexity while maintaining reliable isolation.
Solution Approach 2:
The interlayer dielectric material serves multiple functions: it provides electrical isolation between contacts, fills the contact cut region, and forms part of the overall contact structure geometry. This multi-functionality reduces the need for additional dedicated isolation structures, thereby simplifying the overall device architecture while achieving reliable electrical separation.
Data Source
AI summary
A semiconductor IC structure includes an upper transistor and lower transistor each with respective source/drain (S/D) regions. The upper S/D region includes a S/D cut sidewall. A first frontside contact is in contact with the upper S/D region and includes a first conductive portion with a first cut sidewall that is substantially coplanar with the S/D cut sidewall. A second frontside contact is in contact with the lower S/D region and includes a second conductive portion with a second cut sidewall. A contact cut region may be between the first and second frontside contacts. This structure may be fabricated at least in part by forming a monolithic frontside contact against the lower S/D region and against the upper S/D region and simultaneously separating the monolithic frontside contact into the first frontside contact and the second frontside contact while removing a portion of the upper S/D region.