Frontside-Formed Backside Source/Drain Contacts for GAA Interconnect Scaling
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Solution Overview
Problem
Existing integrated circuit structures face challenges with scaled interconnects, particularly in gate-all-around (GAA) transistor architectures, where forming backside source or drain contacts can damage surrounding materials, impacting yield and performance.
Innovation Solution
The formation of backside source or drain contacts is achieved by creating trenches from the frontside during gate spacer deposition, using sacrificial dielectric material that is later replaced with conductive material, ensuring self-alignment and minimizing damage to surrounding materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If backside source or drain contacts are formed using conventional methods, then interconnect congestion is alleviated, but surrounding materials such as gate stacks and spacers are damaged
Solution Approach 1:
Trenches for backside contacts are formed from the frontside during gate spacer deposition, and sacrificial dielectric material is deposited within these trenches at the same time. This preliminary action ensures that the trench geometry and sacrificial material are in place before backend processing, enabling self-aligned contact formation without damaging surrounding structures
Solution Approach 2:
Sacrificial dielectric material is introduced as an intermediary substance that temporarily occupies the contact trenches. This sacrificial material can be selectively removed from the backside without affecting the gate stack or spacers, and then replaced with conductive material to form the final backside contacts
2Productivity
If frontside interconnects are used for power and signal routing, then device functionality is achieved, but congestion occurs due to high density of scaled interconnect features
Solution Approach 1:
The patent introduces backside contacts as a second dimension for interconnect routing. By forming source or drain contacts on both the frontside and backside of the device layer, the patent creates dual-sided interconnect access, effectively doubling the routing capacity and alleviating congestion in scaled devices
3Ease of manufacture
If trenches are formed from the backside for contact formation, then direct access is achieved, but surrounding materials are damaged during processing
Solution Approach 1:
Instead of forming trenches from the backside where damage would occur, the patent inverts the approach by forming trenches from the frontside during gate spacer deposition. The trenches extend through the device layer to the backside, but the formation process occurs from the front, protecting the backside surrounding materials from damage
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
An integrated circuit structure includes a device layer including a plurality of devices. The plurality of devices includes (i) a plurality of source and drain regions, (ii) a plurality of gate stacks, and (iii) a plurality of gate spacers, each gate spacer separating a corresponding source or drain region from a corresponding gate stack, the gate spacers comprising a first dielectric material. A first source or drain contact is coupled to a frontside of a first source or drain region of the plurality of source or drain regions. A second dielectric material is coupled to a backside of the first source or drain region. A second source or drain contact is coupled to a backside of a second source or drain region of the plurality of source or drain regions. In an example, the first dielectric material and the second dielectric material comprise the same elemental constituents.