FSK Receiver Decimation and Timing Correction With Fractional Resampling
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Solution Overview
Problem
Conventional digital decimation filters in wireless communication equipment are overly complex and inflexible, struggling to accommodate variations in sampling rates and timing errors, which limits their ability to efficiently process analog-to-digital signals and correct for timing drift.
Innovation Solution
An arbitrary rate digital decimation architecture employing a cascaded sequence of power-of-two decimation filters connected to a delta-sigma fractional decimator, allowing for dynamic adjustments in sampling rates and timing corrections through a fractional resampler that can operate as either a decimator or interpolator, using a delta-sigma modulator and limited integrator to generate pulse commands for clock adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fixed decimation filters are used, then the decimation rate is predetermined and stable, but the system cannot flexibly accommodate variations in sampling rate and timing errors
Solution Approach 1:
The patent implements a dynamic decimation filter system where the decimation rate can be adjusted in real-time based on timing error corrections. The system uses a variable decimation rate mechanism that adapts to changing sampling conditions, allowing the receiver to maintain synchronization without requiring multiple fixed-rate filters. This dynamic adjustment capability directly resolves the contradiction by enabling sampling rate flexibility while managing complexity through a unified adaptive structure.
Solution Approach 2:
The system changes the decimation parameter dynamically based on detected timing errors. By modifying the decimation rate parameter in response to timing drift, the system achieves adaptability to varying sampling conditions. This parameter change approach allows a single filter structure to handle multiple sampling rate requirements, avoiding the need for multiple fixed filters and thereby managing complexity while improving versatility.
2Adaptability or versatility
If multiple reference crystal frequencies are used to meet de-sensing requirements, then sampling rate flexibility is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent employs a universal reference oscillator that serves multiple functions: it provides the base clock signal and enables variable decimation rates through digital control. Instead of using multiple crystal frequencies, the system uses a single reference oscillator combined with a programmable decimation engine that can achieve different effective sampling rates. This multi-functional approach resolves the contradiction by providing decimation sampling rate flexibility through software/digital control rather than hardware multiplicity, thereby reducing device complexity and fabrication cost.
3Adaptability or versatility
If timing error corrections are applied over large ranges, then the system can handle large over-the-air packets, but conventional filters cannot provide unbounded correction ranges
Solution Approach 1:
The patent segments the timing correction function into multiple stages: a coarse correction stage that handles large timing drifts and a fine correction stage that provides precise adjustments. This segmentation allows the system to achieve both large correction ranges and high accuracy. The variable decimation filter works in conjunction with these staged corrections, providing the flexibility needed for unbounded timing correction while maintaining reliability through progressive refinement of the correction.
Solution Approach 2:
The system uses dynamic adjustment of the decimation rate in response to timing error magnitude. For large timing errors, the system applies larger decimation adjustments, and for smaller errors, it uses finer adjustments. This dynamic response enables the system to handle both large over-the-air packets and maintain timing correction accuracy across the full range of corrections, resolving the contradiction between correction range and accuracy.
Data Source
AI summary
An arbitrary rate digital decimator filter (204) and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages (205, 207) connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage (211) which generates a second filtered digital signal with delta-sigma modulator (310) and a limited integrator stage (320) connected to receive a first control (301) word and a feedback clock signal (305) with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands (303) to a timing shift filter (340) which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.