FSK Demodulator Using Counter-Timer Pulse Grouping
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Solution Overview
Problem
Conventional FSK demodulation methods require high-speed counter/timer clock frequencies, which are difficult to implement with current microcontroller technology, especially for frequencies close together as specified by the Wireless Power Consortium WPC-QI standard.
Innovation Solution
A counter/timer-based FSK demodulator that processes a succession of pulses, measuring the duration of a pre-chosen number of consecutive pulses and comparing these values with a threshold only during expected frequency changes, reducing system clock speed requirements and improving noise tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional counter/timer circuitry is used to resolve FSK frequencies, then frequency resolution is achieved, but the required clock frequency becomes unachievable with current microcontroller technology
Solution Approach 1:
The patent applies preliminary action by pre-defining a set of possible frequency values before measurement begins. The counter/timer accumulates cycle counts for each predefined frequency candidate simultaneously, and the frequency with the highest count is selected as the detected frequency. This eliminates the need for high-speed sequential comparison and enables operation at lower clock frequencies achievable with current microcontrollers.
Solution Approach 2:
The patent segments the frequency measurement process by dividing it into discrete frequency bins corresponding to predefined frequency values. Instead of measuring frequency continuously or comparing against a single threshold, the signal is analyzed across multiple frequency segments simultaneously, allowing accurate frequency resolution without requiring proportionally high clock speeds.
2Measurement precision
If the FSK frequencies are close together as specified by WPC-QI standard, then better frequency discrimination is achieved, but the required counter/timer clock frequency increases to 128 MHz which is difficult to implement
Solution Approach 1:
The patent resolves the implementation difficulty by pre-defining all possible frequency values in a lookup table before operation. During signal analysis, the system accumulates cycle counts for each predefined frequency candidate and selects the frequency with the maximum count. This approach enables accurate discrimination of closely spaced frequencies (31.25 ns difference per bit per 512 cycles) without requiring high-speed microcontrollers, as the computationally intensive frequency analysis is replaced by simple counting and comparison operations.
3Measurement precision
If a higher clock frequency is used to resolve close FSK frequencies, then frequency resolution improves, but power consumption increases
Solution Approach 1:
The patent changes the operational parameters by using a lower clock frequency combined with a software-based frequency analysis algorithm. Instead of relying on high-speed hardware counters, the system uses a microcontroller with a lower clock frequency to accumulate cycle counts over multiple periods and determine frequency through software comparison. This parameter change significantly reduces power consumption while maintaining the ability to resolve closely spaced FSK frequencies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables FSK demodulation with readily achievable system clock frequencies, reducing power consumption and software iterations while maintaining compatibility with the Wireless Power Consortium standard, and allowing for cost-effective parsing of FSK-modulated message packets.
Implementation Method 1
a first comparator for processing the received FSK signal to produce a FSK pulsed waveform comprising a succession of pulses
Implementation Method 2
a counter/timer, operably coupled to the first comparator, for receiving the FSK pulsed waveform and for determining measured count values of a duration of a pre-chosen number, n, where n is less than N, of consecutive pulses of the FSK pulsed waveform
Implementation Method 3
a second comparator, operably coupled to the counter/timer, for receiving the measured count values and for comparing the measured count values with a pre-determined threshold value and for outputting a bit value of '0' or '1' depending on the comparison
Data Source
AI summary
A demodulator suitable for demodulating binary FSK signals having a small difference between carrier frequencies uses a counter-timer technique for timing a fixed number FSK cycles and comparing a count value with a threshold when a frequency change is expected. By grouping a number of FSK pulses (or cycles) together in one measurement, speed requirements on the system clock used for the counter/timer measurements can be relaxed and tolerance to noise is also improved. The demodulator is particularly suitable for wireless charging applications.