Automatic Frequency Correction for FSK Receivers
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Solution Overview
Problem
Existing automatic frequency correction mechanisms in receivers struggle to robustly synchronize with transmitters in noisy environments, particularly in Frequency Shift Keying (FSK) systems, due to jitter introduced by noise affecting the alignment of clock edges.
Innovation Solution
A method and circuit that generate I and Q pulse signals based on the leading edges of baseband signals to create a local clock correction signal, using a frequency corrector to compare these signals and adjust the local frequency reference, with a retiming unit to delay and align pulses with the bitclock signal, and frame synchronization to manage the frequency correction and retiming units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a discrete AFC block is used after the demodulator, then frequency synchronization can be achieved, but the system becomes vulnerable to noise-induced jitter that affects clock edge alignment
Solution Approach 1:
The invention segments the frequency correction function into two distinct units: a frequency corrector that processes I and Q pulse signals to correct frequency errors, and a retiming unit that separately handles clock edge alignment. This segmentation allows each unit to specialize in one aspect of synchronization, making the overall system more robust against noise-induced jitter while maintaining frequency synchronization reliability.
Solution Approach 2:
The invention introduces I and Q pulse signals as intermediary elements between the demodulator and the frequency correction mechanism. These pulse signals serve as mediators that capture edge timing information in a noise-resistant manner, allowing the frequency corrector to make accurate frequency adjustments without being directly affected by noise-induced jitter on the original clock edges.
2Ease of operation
If traditional PLL-based AFC is used, then clock alignment can be achieved, but the device complexity increases due to the discrete block architecture
Solution Approach 1:
The invention merges the frequency correction and retiming functions into an integrated architecture that shares common resources such as the local signal generator and pulse signal generation logic. By combining these functions and eliminating the need for a separate discrete AFC block, the system achieves clock alignment capability while reducing overall device complexity.
Solution Approach 2:
The local signal generator and pulse signal generation circuitry serve multiple functions: they generate the local frequency reference for downconversion, generate the bitclock signal for sampling, and provide timing references for both frequency correction and retiming operations. This multi-functionality reduces the need for separate dedicated circuits, thereby reducing device complexity while maintaining full clock alignment capability.
Data Source
AI summary
A receiver front end receives a local frequency reference signal and a Frequency Shift Keying modulated signal comprising a synchronisation sequence, and downconverts the Frequency Shift Keying modulated signal to provide baseband in-phase and quadrature signals. A pulse generator receives the in-phase and quadrature signals, generates an in-phase pulse signal ILEAD comprising pulses aligned with edges of the baseband in-phase and quadrature signals when the baseband in-phase signal leads the baseband quadrature signal, and generates a quadrature pulse signal QLEAD comprising pulses aligned with edges of the baseband quadrature and in-phase signals when the baseband quadrature signal leads the baseband in-phase signal. A frequency corrector receives the in-phase and quadrature pulse signals during receipt of the synchronisation sequence, compares the pulse signals to a target, and generates a control signal for controlling the local signal generator in dependence upon the result of the comparison.