FSK Receiver Circuit with PLL Demodulator and AFC
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital radio receivers face challenges in improving reception characteristics due to the need to reduce frequency and DC offset impacts, which complicates the circuit and increases costs, especially when using inexpensive ICs for PLL modulation without expensive AD converters or DSPs.
Innovation Solution
A receiver configuration with a signal generator, mixer, PLL demodulator, detector, and AFC unit that operates in both preparation and reception modes to detect and correct frequency offsets and gain settings, allowing for M-ary FSK demodulation without expensive components, using a single signal generator for calibration and reception.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequency offset correction and DC offset removal circuits are added to improve reception characteristics, then reception quality is improved, but circuit complexity and cost increase
Solution Approach 1:
The patent combines multiple functions (frequency offset correction, DC offset removal, gain control) into a single integrated receiver circuit. The mixer output is simultaneously used for AFC processing, DC offset removal via correlation processing, and FSK demodulation, eliminating the need for separate dedicated circuits for each function.
Solution Approach 2:
The receiver circuit performs multiple operations using the same hardware components. The correlation processing unit uses the reference frame synchronization word for both DC offset removal and frequency offset detection. The single receiver structure handles FSK demodulation, AFC, and gain control without requiring additional specialized circuits.
2Measurement precision
If multiple separate circuits are used for frequency offset correction and DC offset removal, then reception accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges frequency offset detection and DC offset removal into a single receiver structure. Both functions utilize the same mixer output signal and reference frame synchronization word, allowing accurate frequency offset detection without requiring separate expensive circuits.
3Ease of manufacture
If the circuit is simplified to reduce cost, then manufacturing cost decreases, but reception characteristics deteriorate
Solution Approach 1:
The receiver performs self-calibration using its own transmitted signal. The correlation processing unit uses the reference frame synchronization word that is already part of the transmitted signal to automatically detect and correct frequency offsets and remove DC offsets, eliminating the need for external calibration equipment or additional correction circuits.
4Object-affected harmful factors
If complex processing is applied to reduce frequency offset impact, then frequency offset resistance is improved, but processing time increases
Solution Approach 1:
The receiver performs frequency offset detection and correction during the reception process itself using the reference frame synchronization word. The correlation processing is done continuously as signals are received, allowing real-time frequency offset compensation without requiring separate pre-processing or post-processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies the process, improves reception characteristics, and reduces errors, enabling accurate M-ary FSK demodulation with a low error rate and high sensitivity, while maintaining a cost-effective and adaptable solution to temperature and IC variations.
Implementation Method 1
a mixer that is connected to the signal generator and an antenna and outputs a signal at an intermediate frequency
Implementation Method 2
a PLL demodulator that subjects the signal at the intermediate frequency from the mixer to PLL demodulation
Implementation Method 3
a detector that detects an amount of shift occurring in the PLL demodulator
Implementation Method 4
an AFC unit that detects a frequency offset in the signal from the PLL demodulator and causes the signal generator to make a correction for the frequency offset detected
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A mixer is connected to a signal generator and an antenna and outputs a signal at an intermediate frequency. A PLL demodulator subjects the signal at the intermediate frequency from the mixer to PLL demodulation. An amplifier amplifies a signal from the PLL demodulator. A detector detects an amount of shift occurring in the PLL demodulator. A detector detects a gain of the amplifier. An FSK demodulator subjects a signal from the amplifier to FSK demodulation. An AFC unit detects a frequency offset in the signal from the amplifier and causes the signal generator to make a correction for the frequency offset detected.