Finite State Machine Interface Arbitration for Flash EEPROM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing finite state machine designs for digital and digital-analog integrated circuits face challenges with complex specifications, including wide windows not sensitive to commands, complex design, difficulty in reproduction, area occupation, and testability, due to the need for multiple clocks and resets, which hinder optimization and lead to increased error probabilities.
Innovation Solution
A state machine operating with a single CLK command and a single reset, managed by an arbitration structure that detects and cues requests, storing commands when the machine is busy and filtering unnecessary ones, allowing only valid commands to be processed when the machine is available, effectively reducing stress and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clocks and resets are used in finite state machine designs, then the machine can handle complex specifications and multiple command sources, but the design complexity increases and error probability rises
Solution Approach 1:
An arbitration structure is introduced as an intermediary component between multiple command sources and the finite state machine. This arbiter manages clock signals and reset signals, selecting which command source controls the FSM at any given time. The arbitration logic evaluates priority levels and current state to determine command acceptance, thereby reducing the complexity burden on the FSM itself while maintaining the ability to handle complex specifications through structured command management.
2Adaptability or versatility
If multiple clocks and resets are used in finite state machine designs, then the machine can interface with multiple internal circuits, but the silicon area occupation increases
Solution Approach 1:
Multiple clock and reset control functions are merged into a single arbitration structure that centrally manages all command sources. Instead of implementing separate control logic for each internal circuit interface, the arbiter consolidates these functions by maintaining priority registers and control logic that can route commands from any source through a unified interface to the FSM, thereby reducing overall silicon area while preserving multi-circuit interfacing capability.
3Productivity
If multiple clocks and resets are used in finite state machine designs, then the machine can process simultaneous commands from different sources, but testability becomes difficult
Solution Approach 1:
The command processing system is segmented into distinct functional modules: the arbitration structure that manages command sources, priority registers that determine command selection, and the FSM that executes commands. This segmentation allows testers to independently verify each module's functionality. The arbiter can be tested for correct priority-based selection, priority registers for proper command routing, and the FSM for accurate command execution, thereby improving testability while maintaining simultaneous command processing capability.
4Productivity
If the finite state machine processes commands continuously, then productivity is high, but the risk of command loss or system halt increases
Solution Approach 1:
The arbitration structure performs preliminary evaluation of incoming commands before they reach the FSM. It assesses whether the FSM is currently busy processing a command and whether the new command has appropriate priority. Commands are buffered or rejected based on this preliminary assessment, preventing command loss while avoiding system overload. This preliminary filtering action maintains high productivity by accepting valid commands while protecting reliability by rejecting commands that would cause conflicts or losses.
Data Source
AI summary
An interface is provided for an integrated system that includes internal circuits, with each internal circuit functioning based upon its own clock. The interface includes a finite state machine for managing asynchronous and independent interactions between the internal circuits and external circuits. The finite state machine functions based upon a unique clock and a unique reset. The interface also includes an arbitration circuit connected to the finite state machine for receiving input signals for the finite state machine. The arbitration circuit includes a memory buffer for storing signals generated by the internal circuits when the finite state machine is performing an evaluation. The interface may be used to form a command interpreter of a non-volatile memory device.


