Finite State Machine Generation for Asynchronous Callback Testing

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Solution Overview

Problem

Testing of software systems with asynchronous callback behavior is challenging due to the non-determinism of thread execution, making it difficult to model and verify the correct behavior of these systems.

Innovation Solution

The development of tools and techniques that generate finite state machines (FSMs) to model asynchronous callbacks, allowing for the creation of FSMs that represent software systems with asynchronous behavior, enabling more effective testing and improving the performance and reliability of such systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional testing methods are used for asynchronous callback systems, then testing coverage is limited, but the complexity of modeling and verifying correct behavior increases significantly

Engineering Contradiction:
Improvetesting coverageVSAvoidmodeling complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary component that translates asynchronous callback behavior into synchronous state machine transitions. This mediator layer allows conventional testing methods to be applied to asynchronous systems by converting the complex non-deterministic callback patterns into deterministic FSM states and transitions, thereby improving testing coverage without directly increasing modeling complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates a copy or representation of the asynchronous system's behavior in the form of a finite state machine model. This FSM copy captures the essential state transitions and callback patterns without requiring direct testing of the complex asynchronous thread execution, enabling simplified verification while maintaining testing effectiveness.

Inventive Principle:
Principle #26Copying

2Measurement precision

If detailed modeling of asynchronous thread execution is attempted, then behavior verification improves, but the difficulty of creating and maintaining models increases

Engineering Contradiction:
Improvebehavior verification accuracyVSAvoidmodel creation difficulty
Core Design Contradiction:
Measurement precisionVSDifficulty of detecting and measuring

Solution Approach 1:

The patent segments the complex asynchronous system into discrete, manageable state transitions within a finite state machine. By dividing the continuous asynchronous execution into distinct states and transitions, the system achieves precise behavior verification through manageable model components that are easier to create and maintain than a monolithic detailed model.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter representation from detailed thread execution traces to abstracted FSM state parameters. This parameter transformation maintains verification accuracy by preserving essential behavioral characteristics while reducing model creation difficulty through simplified state descriptions and transition conditions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7500149B2Generating finite state machines for software systems with asynchronous callbacks
Publication Date: 2009.03.03 MICROSOFT TECHNOLOGY LICENSING LLC
  • US7500149B2 patent drawing
  • US7500149B2 patent drawing
  • US7500149B2 patent drawing

AI summary

Techniques and tools for generating finite state machines (“FSMs”) for a software system with asynchronous callbacks are described. For example, method invocations in a model of the software system are partitioned into observable and controlled method invocations. The controlled method invocations are those which can be run from a test harness while the observed method invocations are those which are observed asynchronously as they are invoked in the system. An FSM is created with observation and control nodes such that observable transitions are found from observation nodes and controlled transitions are found from control nodes. If a state of the model contains both controlled and observable invocations, a timeout transition is added to the FSM to give an implementation time to come up with an observed method invocation before continuing to controlled invocations.