Third-Order Clock Recovery Circuit With FSM Jitter Cancellation
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Solution Overview
Problem
Conventional clock and data recovery (CDR) circuits in digital communication systems, particularly those using first or second order digital filters, are inadequate in canceling residual jitter, especially when the receiver clock is generated based on spread-spectrum, leading to performance and stability issues.
Innovation Solution
A novel CDR circuit employing a third order finite state machine (FSM) with three accumulators connected in series, which generates a third order phase code to completely cancel residual jitter, improving jitter tolerance and system stability by rotating the clock signal based on this phase code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a first order or second order digital filter is used in the CDR circuit, then the device complexity is reduced, but the ability to cancel residual jitter is insufficient
Solution Approach 1:
The patent changes the order parameter of the digital filter from first or second order to third order. This parameter change enables the filter to completely cancel residual jitter in the CDR circuit, directly resolving the contradiction between jitter cancellation capability and device complexity by selecting an optimal filter order that provides sufficient performance without excessive complexity
Solution Approach 2:
The patent implements a feedback mechanism where the third order digital filter continuously monitors and adjusts the clock signal based on detected jitter. The feedback loop processes phase error signals through the higher order filter to generate corrected clock phases, enabling complete cancellation of residual jitter while maintaining system stability
2Reliability
If a third order digital filter is used to completely cancel residual jitter, then the reliability improves, but the device complexity increases
Solution Approach 1:
The patent optimizes the filter order parameter to exactly third order, which is the minimum order required to completely cancel residual jitter. This precise parameter selection achieves the desired reliability improvement while avoiding the excessive complexity that would result from higher order filters, resolving the contradiction between performance and complexity
Solution Approach 2:
The patent replaces complex analog jitter cancellation mechanisms with a digital third order filter implementation. This substitution achieves complete jitter cancellation through digital signal processing while maintaining manageable device complexity through the use of standard digital filter architectures
Data Source
AI summary
Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.