FSM-Based Code-to-Gate Mapping for FPGA Packet Processing
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Solution Overview
Problem
Designing and programming integrated circuits, such as FPGAs and ASICs, is a difficult task due to the complexity of mapping computer code to wires and gates, which requires optimizing the number of states in finite state machines for efficient data processing.
Innovation Solution
A method and system for mapping computer code to wires and gates by generating a finite state machine (FSM) and optimizing it to minimize the number of states, then translating it into a wires and gates representation for configuring field-programmable gate arrays, where combinatorial logics not dependent on input wires are stored in shift registers and those dependent on input wires are stored in flip-flops, optimizing the number of gates and wires based on data transmission protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a detailed wires and gates representation is generated from computer code, then the integrated circuit can be configured to process data packets efficiently, but the complexity of mapping and configuring the circuit increases
Solution Approach 1:
The patent introduces a finite state machine (FSM) as an intermediary representation between high-level computer code and the detailed wires-and-gates configuration. The FSM serves as a mediating layer that captures the control flow and state transitions of the code in a structured format, making it easier to translate into hardware configuration while reducing mapping complexity.
Solution Approach 2:
The patent extracts the control logic from the computational logic by representing it separately as a finite state machine. This separation allows the control flow to be optimized and minimized independently from the data processing logic, reducing the overall complexity of the mapping process while maintaining data processing efficiency.
2Device complexity
If the number of states in the finite state machine is minimized, then the number of gates and wires required decreases, but the optimization process becomes more complex
Solution Approach 1:
The patent applies parameter changes by transforming the FSM representation to enable state minimization. This involves changing the parameters of the state representation and transition conditions to facilitate optimization algorithms that can reduce the number of states while preserving the functional behavior, thereby reducing the number of gates and wires needed.
Solution Approach 2:
The patent performs preliminary optimization of the finite state machine before generating the wires-and-gates representation. By minimizing the number of states in advance, the subsequent hardware generation process becomes simpler and requires fewer resources, even though the optimization itself adds a preliminary step to the manufacturing process.
3Reliability
If combinatorial logics are stored in flip-flops when they depend on input wires, then data dependency is preserved, but the number of storage elements increases
Solution Approach 1:
The patent applies local quality by differentiating the storage mechanism based on the specific characteristics of each combinatorial logic. Instead of using a uniform storage approach, the system selectively places combinatorial logics in shift registers or flip-flops depending on their input dependencies. This localized optimization preserves data dependency where needed while minimizing the total number of storage elements.
Data Source
AI summary
Methods and systems for mapping computer code to wires and gates are disclosed. An example method may include acquiring a code written in a programming language and generating, based on the code, a finite state machine (FSM). The method may further include generating, based on the FSM, a wires and gates representation, the wires and gates representation including a plurality of wires and a plurality of combinatorial logics. The method may further include configuring, based on the wires and gates representation, a field-programmable gate array. Input of each of the plurality of wires may represent a symbol selected from a set of symbols of a structured data packet. The size of the symbol can be equal to a number of bits of the structured data packet transferred per a clock cycle according to a data transmission protocol.