Finite State Machine Timing Optimization via Control Bit Logic
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Solution Overview
Problem
Current optimization methods for finite state machines (FSMs) in circuit designs often fail to improve the maximum frequency (Fmax) attainable by the overall system, as they primarily focus on reducing delays in the logic that calculates the current state, neglecting the delays from the FSM to downstream registers and output terminals, which requires manual recoding and recompilation in hardware description language (HDL) to achieve desired performance.
Innovation Solution
A method that automates the process of reducing delays from FSMs to downstream registers and output terminals by generating control bit logic and adding a control bit register in parallel with the next state logic and current state bit registers, determining worst-case delays before and after changes, and saving or undoing updates based on delay improvements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If optimization focuses on decreasing delay in FSM current state logic, then FSM internal timing is improved, but overall system Fmax is not improved due to persistent delays from FSM to downstream registers
Solution Approach 1:
The patent segments the timing optimization into two distinct phases: (1) optimizing FSM internal state logic delays, and (2) optimizing downstream register delays. By separating these optimization tasks and applying different strategies to each phase, the system addresses the root cause of timing issues without compromising either FSM functionality or overall performance.
Solution Approach 2:
The patent performs preliminary optimization of the FSM current state logic to establish a baseline, then subsequently optimizes the downstream register timing paths. This sequential approach allows the system to build upon previous optimizations and achieve cumulative improvements in overall Fmax.
2Productivity
If manual HDL recoding and recompilation is performed to optimize downstream register delays, then system Fmax can be improved, but the process is painstaking and prone to errors
Solution Approach 1:
The patent implements automated optimization tools that self-adjust the HDL code and timing parameters without requiring manual intervention. The system automatically generates optimized downstream register logic, performs timing analysis, and applies corrections, thereby eliminating the need for painstaking manual recoding and reducing human error.
Solution Approach 2:
The patent incorporates iterative feedback loops where timing analysis results are automatically fed back into the optimization process. The system continuously monitors timing parameters, identifies bottlenecks, and applies corrections automatically, creating a closed-loop optimization system that improves Fmax without manual HDL recoding.
3Productivity
If downstream register delays are optimized by adding control bit logic and registers, then Fmax is improved, but netlist complexity increases
Solution Approach 1:
The patent merges the control bit logic with existing FSM structure by integrating it into the next state logic computation. Rather than adding completely separate control mechanisms, the system combines control bit generation with the existing state transition logic, thereby reducing overall netlist complexity while still achieving timing optimization.
Solution Approach 2:
The control bit registers and logic serve multiple functions: they optimize timing for downstream registers, maintain FSM state information, and enable flexible control of register updates. This multi-functionality reduces the need for separate dedicated timing control circuits, thereby limiting the increase in netlist complexity.
Data Source
AI summary
In one approach for improving timing in an electronic circuit design having a finite state machine (FSM), control bit logic is generated based on next state logic of the FSM that generates current state bits of the FSM. The control bit logic and a control state bit are added to operate in parallel with the next state logic and the current state bit registers, and the output signal from the control bit register replaces selected logic in logic downstream from the FSM and current state bit registers. If a worst case delay is improved with the design having the control bit logic and control state bit, the modified circuit design is saved for evaluating other possible timing improvements. Otherwise, the modification is discarded.