Voltage Regulator FSM Control for Droop Recovery and Loop Stability
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Solution Overview
Problem
Existing voltage regulators face challenges in operating efficiently, cost-effectively, and stably due to tradeoffs between voltage converter efficiency optimizations and transient droop mitigation, leading to issues like high-frequency limit cycle oscillations, insufficient mitigation, and behavioral variation across conditions.
Innovation Solution
A parallel current source (PCS) is used in conjunction with a finite state machine (FSM) and filtered comparators to augment current during droop conditions, coordinating loop interactions with a buck converter's feedback mechanism to mitigate droop while maintaining loop stability, using power management information and digital calculations to optimize modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If voltage converter efficiency optimizations are implemented, then power delivery efficiency is improved, but transient droop mitigation becomes insufficient
Solution Approach 1:
The patent segments the current source into multiple independent current sources, each controlled by its own comparator and feedback loop. This segmentation allows each current source to independently respond to specific droop conditions, improving transient response while maintaining overall efficiency. The divided architecture enables parallel operation of multiple current paths.
Solution Approach 2:
The patent implements dynamic control where the current sources and comparators actively adjust their operation based on real-time voltage droop detection. The system transitions between different operational states (normal operation, droop detection, droop mitigation) based on feedback signals, enabling adaptive response to varying load conditions while maintaining efficiency.
2Stability of the object's composition
If droop mitigation is enhanced, then voltage stability is improved, but high-frequency limit cycle oscillations occur
Solution Approach 1:
The patent applies preliminary anti-action by having comparators continuously monitor voltage levels and trigger current source activation before severe droop occurs. The system detects undershoot conditions and preemptively adjusts current delivery to counteract potential oscillations, preventing limit cycle behavior while maintaining voltage stability.
Solution Approach 2:
The patent implements multiple feedback loops where comparators continuously sense output voltage and provide feedback signals to control current sources. This feedback mechanism enables real-time adjustment of current delivery to maintain stable voltage while preventing the conditions that lead to high-frequency oscillations through proper damping control.
3Reliability
If parallel current source is added, then droop mitigation is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple current sources and comparators into a coordinated system where components share common control signals and feedback paths. By combining the droop detection functionality across multiple parallel current sources, the system achieves improved droop mitigation while reducing overall complexity through shared infrastructure rather than fully independent control circuits.
Solution Approach 2:
The patent designs the parallel current sources and comparators to serve multiple functions: normal current delivery, droop detection, droop mitigation, and oscillation prevention. Each comparator and current source can operate in different modes depending on system conditions, reducing the need for separate dedicated circuits for each function and thereby lowering overall device complexity.
Data Source
AI summary
Embodiments herein relate to a voltage regulator (VR) which includes a main current source (MCS), a parallel current source (PCS) which is activated when a voltage droop is detected, and a finite state machine (FSM) to manage a recovery from the voltage droop. The FSM can have a Droop state in which a droop is detected in the output voltage of the VR and the PCS provides an output current to an output node of the VR, a PCS ramp down state in which the output current of the PCS ramps down while the MCS has a boosted set point, and a voltage identifier (VID) boost ramp down state in which the set point of the MCS ramps down from the boosted set point.