State Machine Engine Programming for Hierarchical Pattern Recognition

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Solution Overview

Problem

Conventional computers face inefficiencies in performing complex data analysis, particularly in pattern recognition tasks, due to the increasing volume of data and number of patterns to be detected, leading to processing bottlenecks and delays.

Innovation Solution

A state machine engine with finite state machine lattices arranged in a hierarchical parallel configuration, allowing multiple finite state machines to analyze the same data in parallel, thereby increasing processing speed and efficiency in recognizing patterns within high-bandwidth data streams.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional von Neumann based computers are used for complex data analysis, then the system structure is simple and easy to manufacture, but the processing speed and efficiency deteriorate due to sequential processing bottlenecks

Engineering Contradiction:

Improvedata analysis speedVSAvoidsystem architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The system segments the data analysis task into multiple parallel finite state machines, each capable of independently processing different aspects of pattern recognition. This segmentation enables concurrent processing of multiple patterns simultaneously, dramatically improving data analysis speed while maintaining manageable complexity through modular design

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential single-dimensional processing to parallel multi-dimensional processing by organizing finite state machines in hierarchical layers. Lower layers process raw signals while higher layers analyze outputs from lower levels, creating a multi-dimensional processing architecture that improves productivity without proportionally increasing complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the number of patterns to be detected increases, then the comprehensiveness of pattern recognition improves, but the processing delay increases due to sequential searching

Engineering Contradiction:

Improvepattern detection capabilityVSAvoidprocessing delay

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent merges multiple pattern detection functions into a unified parallel processing architecture where multiple finite state machines operate simultaneously on the same data stream. This combining approach allows the system to detect numerous patterns comprehensively without the sequential delays that would occur if each pattern were searched individually

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The system maintains continuous data flow through parallel processing, eliminating idle time between pattern searches. While conventional systems must wait for one pattern search to complete before starting the next, this architecture keeps all processing units continuously engaged with the data stream, reducing overall processing delay while maintaining high adaptability to multiple patterns

Inventive Principle:

Principle #20Continuity of useful action

3Speed

If hardware is designed to search data stream for patterns by distributing data among multiple circuits, then the processing speed improves, but the system cannot effectively perform complex hierarchical data analysis comparable to biological brain

Engineering Contradiction:

Improvedata processing speedVSAvoidcomplex data analysis capability

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements a nested hierarchical structure where finite state machines are organized in layers, with lower-layer machines processing raw signals and higher-layer machines analyzing outputs from lower levels. This nesting enables complex hierarchical data analysis comparable to biological brain organization while maintaining high processing speed through parallel operation at each level

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The finite state machines are designed with universal functionality to perform multiple roles depending on their layer position. Lower-layer machines handle raw signal processing while higher-layer machines perform complex pattern analysis, allowing the same basic computational unit to adapt to different processing requirements and achieve both speed and versatility

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11599770B2Methods and devices for programming a state machine engine

Publication Date: 2023.03.07 MICRON TECHNOLOGY INC

AI summary

A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.