State Machine Engine Overflow Handling in Hierarchical FSM Lattices

The patent divides the pattern recognition task into multiple independent finite state machine (FSM) circuits, each responsible for detecting a specific pattern. These FSMs are organized in a hierarchical structure with multiple levels, where each level processes patterns independently in parallel. This segmentation allows simultaneous pattern detection without sequential processing delays, resolving the contradiction between detection accuracy and processing speed.

The patent transitions from sequential single-dimensional pattern processing to multi-dimensional parallel processing by organizing FSMs in a hierarchical lattice structure with multiple levels and columns. Each FSM operates in its own state space, enabling simultaneous pattern recognition across multiple dimensions of the data stream, thereby achieving both high accuracy and high speed.

The patent implements a hierarchical nested structure where FSMs are organized in levels and columns, with each level containing multiple columns. Each FSM is further divided into state bits and flip-flops. This nested organization allows efficient resource sharing and reduces overall system complexity while maintaining high parallel processing capability. The hierarchical structure enables scalable implementation without linearly increasing hardware complexity.

The patent designs universal FSM circuits that can be configured to detect different patterns through programmable state transitions and input conditions. Each FSM can be reprogrammed to recognize various patterns, reducing the need for dedicated hardware for each pattern and thereby reducing overall system complexity while maintaining high productivity.