Finite State Machine Network Data Stream Processing

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Solution Overview

Problem

Finite state machines (FSMs) struggle to keep pace with high-speed network data streams, such as 10 GbE Ethernet, due to processing rate limitations, leading to inefficiencies in syntax verification and potential cyber-attack detection.

Innovation Solution

The method involves segmenting the network data stream into segments and processing them using multiple sets of identical FSMs, each initialized to different states, allowing for parallel processing and state mapping to enhance processing speed, while ensuring compliance with a predefined syntactic structure and modifying non-compliant data if necessary.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single FSM processes data sequentially, then the processing logic remains simple, but the processing rate cannot keep pace with high-speed network data streams

Engineering Contradiction:
Improveprocessing rateVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The data stream is segmented into multiple segments, and multiple sets of FSMs are employed to process different segments in parallel. Each FSM set processes a specific segment independently, allowing the system to handle high-speed data streams while maintaining manageable complexity through modular processing units

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from single-threaded sequential processing to multi-threaded parallel processing by introducing multiple FSM sets that operate simultaneously on different data segments. This dimensional shift from one processing dimension to multiple dimensions enables throughput scaling without proportionally increasing overall system complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple sets of FSMs process data in parallel, then the processing rate increases, but the device complexity increases

Engineering Contradiction:
Improveprocessing rateVSAvoidnumber of FSM sets
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple identical copies of the FSM are created to form different sets, each processing a separate data segment. This copying approach allows parallel processing to achieve higher throughput while keeping each individual FSM unit simple and reusable, thereby managing overall system complexity through replication rather than complexity multiplication

Inventive Principle:
Principle #26Copying

Solution Approach 2:

Each FSM set is designed to be universal and can process any data segment by initializing to different states corresponding to every different possible state. This multi-functionality allows the same FSM architecture to handle various processing tasks across different segments, reducing the need for specialized processing units for each function

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If FSMs process data at high speed, then the processing rate increases, but the likelihood of syntax verification errors increases

Engineering Contradiction:
Improveprocessing rateVSAvoidsyntax verification accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By dividing the data stream into segments and assigning dedicated FSM sets to each segment, the patent ensures that syntax verification can be performed thoroughly on each segment independently. This segmentation allows high-speed processing while maintaining verification accuracy through focused, dedicated processing of each segment rather than rushing through entire streams

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements feedback mechanisms where the final state of each FSM is recorded and mapped back to the initial state of the next segment. This feedback loop ensures that syntax verification consistency is maintained across segments, allowing high-speed processing while detecting and correcting potential verification errors through state transition validation

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20240388593A1Method and device for processing a network data stream
Publication Date: 2024.11.21 PA KNOWLEDGE
  • US20240388593A1 patent drawing
  • US20240388593A1 patent drawing
  • US20240388593A1 patent drawing

AI summary

According to an aspect of the disclosure there is provided a method of processing a network data stream, comprising: receiving an input data stream; segmenting the received input data stream into a plurality of data stream segments; processing the data stream segments using plural sets of plural identical finite state machines, wherein successive data stream segments are processed by different sets of said plural sets and said plural identical finite state machines comprises finite state machines having initial states corresponding to every different possible state; recording the initial state before processing and a final state after processing, for each state machine; generating an output based on mapping the final state for a data stream segment to a corresponding initial state for a subsequent data stream segment, for each of the plurality of data stream segments.