FSM-Based NRZ Data Transmission for Low-Latency Decoder Circuits
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Solution Overview
Problem
Current data transmission methods in integrated circuits face challenges such as increased design complexity, power consumption, and latency due to the need for complex handshake protocols and additional logic for clock signal generation, particularly in asynchronous design methods like GALS systems, which are inefficient in handling increased wire lengths and noise margin degradation.
Innovation Solution
A data transmission apparatus and method using a Finite State Machine (FSM) logic to encode data into Non-Return-to-Zero (NRZ) format, eliminating the need for assumptions about request and data signal timing and additional clock logic, and employing a 2-phase ternary encoding scheme that converts logic states into different current levels for efficient data transmission without a space state, reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 4-phase handshaking protocol is used for DI data transmission, then data transmission reliability is improved, but latency increases due to the space state being included
Solution Approach 1:
The patent extracts and removes the space state from the traditional 4-phase handshaking protocol, creating a simplified 3-phase protocol that maintains data transmission reliability while reducing latency. The essential handshake functionality is preserved without the unnecessary space state that contributes to delay.
Solution Approach 2:
The patent segments the data transmission process into distinct phases (request, data, acknowledgment) without requiring a separate space state phase. This segmentation allows each phase to be optimized independently, reducing overall latency while maintaining reliability.
2Reliability
If dual-rail encoding is used for data transmission, then noise margin is improved, but the number of wires increases to 2N+1 for N-bit data
Solution Approach 1:
The patent merges multiple signaling functions into a single wire by using ternary encoding that transmits data, request, and control information simultaneously. This consolidation reduces the wire count from 2N+1 to N+1 while maintaining noise immunity through the encoded signal structure.
Solution Approach 2:
The patent changes the encoding parameter from binary dual-rail to ternary encoding, allowing three distinct signal levels to represent different states (data 0, data 1, and request/acknowledgment). This parameter change reduces the number of wires required while preserving noise margin through the use of multiple voltage levels.
3Reliability
If asynchronous design method is used, then clock skew and jitter are eliminated, but design complexity increases and CAD tools are insufficient
Solution Approach 1:
The patent implements self-service asynchronous protocols where each module independently manages its own timing and handshaking without requiring complex global coordination. This self-service approach reduces design complexity by eliminating the need for sophisticated CAD tools while maintaining the benefits of asynchronous operation.
4Reliability
If GALS system is used, then clock skew is solved and stable data transmission is achieved, but the number of transmission wires increases
Solution Approach 1:
The patent merges data and control signals into the same transmission medium by using bidirectional wires that carry both data and request/acknowledgment signals. This merging reduces the total number of wires required in GALS systems while maintaining stable data transmission through the encoded signal protocol.
Data Source
AI summary
Disclosed herein are a data transmission apparatus, a data reception apparatus, and a data transmission method. The data transmission apparatus, the data reception apparatus, and the data transmission method are capable of simplifying the circuit structure of a decoder because an assumption of the time related to a request signal and a data signal is not necessary and an additional logic for generating a clock signal for the decoder is not necessary by using a Finite State Machine (FSM) logic without storing a state via a delay device.