On-Chip Seed Generation Using FSM for BIST
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Solution Overview
Problem
Traditional built-in self-test (BIST) systems for integrated circuits face challenges in achieving high test coverage due to limited seed storage capacity, requiring large on-chip memory or external memory interfaces, which restricts field testing and increases overhead.
Innovation Solution
Implementing a finite state machine (FSM) for on-chip seed generation using simple arithmetic functions, eliminating the need for on-chip seed storage and enabling periodic re-seeding without external memory dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large on-chip memory is used for seed storage, then test coverage is improved, but chip area is increased
Solution Approach 1:
The system generates its own test seeds using an on-chip pseudo-random number generator (PRNG) that operates autonomously. The PRNG uses a small seed storage (e.g., 32 bits) and generates additional seeds through shift-and-add operations, eliminating the need for large external memory while maintaining high test coverage through self-generated test patterns
Solution Approach 2:
The seed storage is segmented into a small on-chip memory (holding only the initial seed) and a pseudo-random number generator that produces additional seeds on-demand. This segmentation allows the system to maintain high test coverage through multiple generated seeds while using minimal chip area for actual seed storage
2Reliability
If external memory interfaces are used for seed storage, then test coverage is improved, but device complexity is increased
Solution Approach 1:
The patent extracts the seed generation function from external memory and implements it directly on-chip using a pseudo-random number generator. This extraction eliminates the need for external memory interfaces and associated control logic, reducing device complexity while maintaining the ability to generate multiple test seeds for high coverage
Solution Approach 2:
The on-chip PRNG serves itself by generating all necessary test seeds internally using simple shift-and-add operations. This self-service approach eliminates dependencies on external memory systems and complex interfaces, achieving high test coverage through autonomous seed generation within the device
3Area of stationary object
If on-chip seed storage is eliminated, then chip area is reduced, but test quality may be compromised
Solution Approach 1:
The system compensates for minimal on-chip seed storage by implementing a self-service pseudo-random number generator that autonomously produces multiple test seeds. The PRNG uses simple shift-and-add operations to generate high-quality pseudo-random sequences, ensuring test quality is maintained despite reduced physical seed storage area
Solution Approach 2:
The patent changes the parameter of seed storage from storing complete test seeds to storing only a small initial seed that is then transformed into multiple test seeds through pseudo-random generation. This parameter change reduces chip area while maintaining test quality through the mathematical properties of the PRNG algorithm
Data Source
AI summary
This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state machine whose states are the seeds as contrasted to storing the seeds in the prior art. These seeds are used to control pseudo-random pattern generation for built-in self-tests. This invention provides a large reduction in chip area in comparison with storing seeds on-chip or off-chip.