Finite-State Machine Security Supervision for Embedded Systems
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Solution Overview
Problem
Existing embedded systems lack effective and fast-reactive security supervision mechanisms, making them vulnerable to various attacks, and existing security supervision methods often introduce latency that can be exploited by attackers.
Innovation Solution
A security supervision system utilizing a finite-state machine with a self-alarm mechanism, error correction codes, and adaptive sensor management to rapidly detect and respond to security threats, enabling fast response times and self-protection mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If security supervision is performed using a coprocessor or time sharing of a processor, then security monitoring capability is provided, but latency is introduced that can be exploited by attackers
Solution Approach 1:
The patent replaces software-based security supervision (coprocessor or time-sharing approaches) with a hardware-based finite state machine implementation. This mechanical substitution eliminates the latency inherent in software execution and context switching, providing both security monitoring capability and fast response times within a single clock cycle.
Solution Approach 2:
The patent creates a simplified copy of the system's operational states using a finite state machine that models the expected behavior of the protected system. This state machine copy can be rapidly compared against actual system states to detect deviations, providing fast security monitoring without the latency of full system simulation or software analysis.
2Reliability
If existing security supervision mechanisms are implemented, then some security monitoring is achieved, but they can themselves be attacked and are insufficient against fast and furtive attacks
Solution Approach 1:
The patent implements self-service through the finite state machine's autonomous operation and self-validation capabilities. The FSM independently monitors system states, validates transitions using error correction codes, and triggers alarms without external intervention, making the security mechanism resistant to attacks that target external control interfaces.
Solution Approach 2:
The patent applies preliminary action by pre-defining all valid system states and transitions in the finite state machine before operation begins. Error correction codes are pre-calculated and stored, enabling the system to immediately detect and respond to unauthorized state transitions without requiring complex real-time analysis, thus preventing attacks rather than merely detecting them.
3Speed
If fast response times within a clock cycle are achieved, then reactivity to attacks is improved, but device complexity increases
Solution Approach 1:
The patent segments the security supervision function into distinct modular components: the finite state machine for state tracking, error correction code generators for validation, and alarm triggers for response. This segmentation allows each component to operate independently and efficiently at clock-speed, achieving fast response times while managing complexity through modular design that can be implemented using standard digital logic building blocks.
Data Source
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AI summary
There is disclosed a system for monitoring the security of a target system (110) with a circuit (120), the target system (110) comprising at least one processor (111) and wherein: the circuit (120) comprises a finite-state machine (122) configured to receive data from one or more sensors (130) distributed in the target system (110), at least one sensor (1303) being located on the processor (111) of the target system (110); the finite-state machine (122) is configured to determine a state output in response to data received from sensors (130); the system monitoring the security based on said state output. Developments describe the use of a self-alarm mechanism comprising an encoder to encode states with redundancy, the application of an error correction code, comparisons with predefined valid encoded states, the triggering of an alarm to the processor, the determination of actions and/or retroactions on sensors and/or diagnostics and countermeasures.