Finite State Machine Debugging for System-on-Chip Hang Conditions
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Solution Overview
Problem
Debugging hang conditions in system-on-chip (SoC) devices is time-consuming and inefficient, as existing methods like watchdog timers cannot detect hardware hang conditions effectively, leading to prolonged debug cycles.
Innovation Solution
A system utilizing finite state machines (FSMs) with a multiplexor, comparators, and logical gates to select timer ticks, compare states, and generate interrupts when sub-systems remain in a hung state for a predetermined period, enabling real-time diagnosis and identification of hardware issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional watchdog timers are used to detect hang conditions, then the system can monitor sub-system states, but the debug time is prolonged and hang conditions cannot be diagnosed in real time
Solution Approach 1:
The system divides the monitoring function into multiple independent Finite State Machines (FSMs), each dedicated to monitoring a specific sub-system. This segmentation allows parallel monitoring of multiple sub-systems simultaneously, enabling real-time detection of hang conditions without the delays associated with traditional sequential watchdog timer approaches.
Solution Approach 2:
The FSMs are pre-configured with state transition criteria and comparison logic before system operation begins. Each FSM continuously compares current sub-system states against expected transitions, allowing immediate detection of hang conditions as they occur rather than requiring post-mortem analysis or periodic sampling.
2Reliability
If FSM-based real-time monitoring is implemented, then hang conditions can be diagnosed immediately, but the device complexity increases with additional components
Solution Approach 1:
A single FSM module design serves as a universal monitoring unit that can be instantiated multiple times for different sub-systems. Each FSM contains all necessary components (state registers, comparators, timer interfaces) to independently monitor any sub-system, reducing overall system complexity compared to implementing custom monitoring logic for each sub-system.
Solution Approach 2:
The FSM structure is nested within the existing sub-system architecture, with FSM state registers integrated into sub-system control logic and comparators embedded within the monitoring framework. This nesting allows the monitoring function to operate transparently without adding external complexity to the overall system structure.
3Adaptability or versatility
If multiple sub-systems are monitored simultaneously, then parallel observability is achieved, but the quantity of components and system complexity increases
Solution Approach 1:
The system employs multiple instances of a universal FSM monitoring module, where each instance can monitor a different sub-system. This approach achieves parallel observability of multiple sub-systems while avoiding the need to design and implement separate monitoring mechanisms for each sub-system, thereby controlling the quantity of unique components required.
Data Source
AI summary
Systems and methods for improving system debugging using finite state machines are described. In one embodiment, the systems and methods includes selecting, by a first multiplexor, a period of a timer tick for one or more blocks of a system on a chip (SoC), comparing, by a first comparator, a current state of the one or more blocks to a previous state of the one or more blocks, and receiving, by a finite state machine (FSM), the result from the first comparator as a first input, receiving a pulse based on the selected period of the timer tick from the first multiplexor as a second input, and based on the first and second inputs generating an output indicating whether the current and previous states remain unchanged after a time of at least two timer ticks. In one embodiment, a result from the first comparator indicates whether the current state equals the previous state of the one or more blocks.