FSM State Buffering for Power-Up Sequence Failure Diagnosis

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Solution Overview

Problem

Current computer systems lack an efficient method to store and retrieve state data from a finite state machine controlling the power-up sequence, making troubleshooting of power-on sequence failures time-consuming and complex due to the inability to determine the exact stage of failure within the power-up sequence.

Innovation Solution

A computer system with a power system control device that includes a finite state machine circuit, a write controller, a storage buffer, and a communication interface, allowing the state of the finite state machine to be stored in a buffer and read by an external controller via an I2C bus, facilitating efficient troubleshooting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the FSM state data is not stored in a buffer for retrieval, then the device complexity is reduced, but the debugging time and complexity increase significantly when power-up sequence failures occur

Engineering Contradiction:
Improvedebugging timeVSAvoidcontrol device complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by storing the FSM state data in a buffer before any failure occurs. The buffer is continuously updated with state information during normal operation, so when a power-up sequence failure happens, the data is already captured and ready for immediate retrieval and analysis, eliminating the need for time-consuming post-failure investigation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary buffer between the FSM and the external debugging interface. This buffer acts as a mediator that captures and holds state information, allowing external controllers to retrieve diagnostic data without adding significant complexity to the core power management logic. The buffer serves as a simple storage intermediary that bridges the FSM and debugging tools.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Difficulty of detecting and measuring

If the FSM state data is stored and made retrievable by external controllers, then the troubleshooting capability is improved, but the device complexity increases due to additional components

Engineering Contradiction:
Improvefailure detection capabilityVSAvoidcontrol device complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent extracts the diagnostic data storage function from the main FSM control logic and places it in a separate buffer. This extraction allows the FSM to remain simple while the buffer handles the complexity of data storage and retrieval. The failure detection capability is improved without significantly complicating the core control device, as the buffer is a standalone component.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent creates a copy of the FSM state data in the buffer rather than modifying the original FSM structure. This copying approach allows external controllers to retrieve diagnostic information without affecting the FSM's primary function. The buffer contains a replicated version of the state data, enabling troubleshooting while keeping the original control logic simple and unchanged.

Inventive Principle:
Principle #26Copying

3Reliability

If a buffer and write controller are added to store FSM states, then the reliability of power-up sequence debugging is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improvedebugging reliabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent uses a simple buffer structure that is inexpensive and straightforward to manufacture. The buffer is designed as a basic storage element without complex features, prioritizing ease of manufacture over advanced functionality. This disposable-like simplicity in the buffer design ensures reliable debugging capability while keeping manufacturing complexity low and production costs down.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS11579673B2Systems and methods for storing FSM state data for a power control system
Publication Date: 2023.02.14 QUANTA COMPUTER INC
  • US11579673B2 patent drawing
  • US11579673B2 patent drawing
  • US11579673B2 patent drawing

AI summary

A system and method for logging state data from a power system control device on a computer system is disclosed. The computer system includes a power system supplying power to the computer system. The power system has a power-up sequence having a plurality of stages. The power system control device is coupled to the power system. The power system control device includes a finite state machine circuit having states corresponding to the stages of the power-up sequence. The control device also has a write controller, a storage buffer, and a communication interface. The write controller writes the state of the finite state machine circuit in the storage buffer. An external controller is coupled to the communication interface and is operable to read the stored state data.