FSM-Based Time Difference Conversion for Low-Noise ADPLLs
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Solution Overview
Problem
Existing time-to-digital converters (TDCs) face limitations in operating at high clock rates and meeting noise performance requirements for low phase-noise synthesis applications, primarily due to reliance on gate delay for time measurement, which restricts time resolution and introduces meta-stability issues.
Innovation Solution
A system utilizing a free-running finite state machine (FSM) and digital low-pass filter to determine the time difference between periodic signals, where the FSM traverses multiple states with constant dwell times, and the digital low-pass filter produces weighted sums of state transition counts to provide a digital representation of the time difference, independent of the reference signal period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate delay is used as the basic unit of time measurement in TDCs, then the device structure is simple, but the time resolution is limited and quantization noise floor increases
Solution Approach 1:
The time measurement process is segmented into multiple coarse measurements using different divider ratios (N=1, N=2, N=4, etc.), where each measurement covers a different time range. The results are combined to achieve fine time resolution without requiring an extremely fast clock, thus resolving the contradiction between simple structure and high precision.
Solution Approach 2:
The patent transitions from a single-dimension time measurement (single clock rate) to multi-dimensional measurement by introducing multiple divider ratios and measurement cycles. This allows achieving high time resolution through temporal and ratio-dimensional expansion rather than simply increasing clock frequency.
2Measurement precision
If high clock rates are used in TDCs, then time resolution may be improved, but the device cannot meet noise performance requirements for low phase-noise synthesis applications
Solution Approach 1:
The patent employs periodic measurement cycles where the FSM traverses through multiple states with different divider ratios in a systematic sequence. This periodic structure allows averaging out noise over multiple cycles while maintaining high effective resolution, thus improving noise performance without requiring excessively high clock rates.
Solution Approach 2:
The patent implements feedback mechanisms where the phase detector output is used to adjust the VCO frequency, and the TDC measurements feed back to the digital filter which refines the frequency control word. This closed-loop feedback system reduces noise accumulation and improves overall noise performance.
3Extent of automation
If known TDCs are implemented in ADPLLs, then the system is all-digital, but the noise performance is substantially worse than phase detectors used in analog PLLs
Solution Approach 1:
The patent performs preliminary coarse frequency acquisition using the FSM with different divider ratios before settling into fine frequency tracking. This preliminary action allows the system to quickly acquire the correct frequency range and reduce initial noise, enabling all-digital operation with noise performance comparable to analog PLLs.
Solution Approach 2:
The patent dynamically changes the divider ratio parameter of the FSM during operation, transitioning from coarse measurement modes (higher ratios) to fine measurement modes (lower ratios). This parameter adaptation allows the all-digital system to optimize noise performance across different operating conditions, matching analog PLL performance.
4Device complexity
If gate delay based TDCs are used, then the basic measurement unit is fixed, but meta-stability issues arise in asynchronous timing
Solution Approach 1:
The patent introduces the FSM as an intermediary mechanism between the asynchronous reference and input signals. Instead of directly comparing signals using fixed gate delays, the FSM provides a structured state transition framework that samples both signals at defined points, eliminating meta-stability issues while maintaining measurement accuracy.
Data Source
AI summary
An apparatus provides a digital representation of a time difference between a periodic reference signal having a reference signal period and a periodic input signal having an input signal period. The apparatus includes a free-running finite state machine (FSM) that traverses a multiplicity of states in a predetermined order, the state having corresponding state vectors, each of which is held for a state dwell time. A timing circuit receives the reference signal, the input signal and the FSM state vectors, and determines a state transition count equal to a number of FSM state transitions that occur during a counting interval, which corresponds to the time difference between the reference and input signals. A digital low-pass filter receives the state transition counts and provides an output value including weighted sums of the state transition counts, proportional to the time difference between the reference and input signal. A period of the FSM is independent of the reference signal period.