Field Side Sub-bitline NOR Flash Array Cell Density
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Solution Overview
Problem
NAND-type flash arrays have smaller cell array areas and lower manufacturing costs compared to NOR-type flash arrays, but they suffer from slower access times and higher operation voltages, while NOR-type flash arrays offer faster read/write speeds and lower voltages but with larger cell areas.
Innovation Solution
The introduction of Field Side sub-bitline NOR (FSNOR) flash arrays, which connect NVM cells using field side sub-bitlines, maintaining cell area density comparable to NAND-type arrays while preserving the advantages of NOR-type flash arrays in read/write speed and low operation voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NOR-type flash arrays are used, then read/write speed and operation voltage are improved, but cell area increases
Solution Approach 1:
The patent divides the bitline connection structure into segments by introducing field side sub-bitlines that connect to side contacts of memory cells, rather than using a single conventional bitline configuration. This segmentation allows for optimized current paths that maintain fast NOR-type access speeds while reducing the overall cell footprint area.
Solution Approach 2:
The patent transitions from a planar bitline connection approach to a three-dimensional configuration by introducing field side sub-bitlines that access side contacts vertically. This dimensional change enables more efficient space utilization, achieving high cell density while preserving the direct electrical connection advantages of NOR architecture for fast read/write operations.
2Area of stationary object
If NAND-type flash arrays are used, then cell area is reduced, but access time increases and operation voltage increases
Solution Approach 1:
By segmenting the bitline connection into field side sub-bitlines that directly connect to side contacts, the patent eliminates the need for complex select transistor chains found in NAND architecture. This segmentation enables direct access to memory cells, dramatically reducing access time while maintaining the compact cell area of NAND-type arrays.
Solution Approach 2:
The field side sub-bitlines act as intermediaries that provide direct electrical connection between the bitlines and memory cell side contacts, eliminating the need for multiple select transistors and complex routing required in NAND architecture. This intermediary structure reduces both access time and operation voltage while preserving compact cell layout.
3Speed
If conventional NOR-type flash arrays are used, then read/write speed is improved, but manufacturing cost increases due to larger cell area
Solution Approach 1:
The patent employs three-dimensional side contact connections via field side sub-bitlines, which enable high-speed NOR-type performance in a reduced two-dimensional footprint. This dimensional transition allows for higher cell density on the same wafer, reducing the number of dies required and thereby lowering per-unit manufacturing costs while maintaining fast read/write speeds.
Solution Approach 2:
The patent changes the geometric parameters of the cell structure by introducing vertical side contact connections and field side sub-bitlines. This parameter change reduces the planar cell area while maintaining the direct electrical connection characteristics necessary for fast NOR-type operation, thereby reducing manufacturing costs through higher wafer utilization.
Data Source
AI summary
Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.