FTJ Memory Cell Circuit for Non-Destructive Low-Power Reading
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Solution Overview
Problem
Existing semiconductor devices face challenges in retaining data for long periods with reduced power consumption and circuit area, particularly in DRAM structures, due to lower electrostatic capacitance and the need for data rewriting.
Innovation Solution
A semiconductor device incorporating transistors and ferroelectric tunnel junction (FTJ) elements with specific dielectric materials like hafnium and zirconium oxide, allowing non-destructive reading and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If capacitor size is reduced to scale down memory cells, then memory capacity increases, but data retention time decreases
Solution Approach 1:
The patent changes the fundamental operating principle from conventional DRAM capacitive storage to FTJ resistive storage with ferroelectric memory effect. By utilizing the high resistance state (HRS) and low resistance state (LRS) of the FTJ element along with its non-volatile memory characteristic, the system achieves long data retention without requiring large capacitor structures, thus resolving the contradiction between small cell size and long retention time.
2Speed
If DRAM structure is used, then fast reading is achieved, but data rewriting is required due to destructive reading
Solution Approach 1:
The patent inverts the conventional DRAM reading mechanism. Instead of destructive reading that requires refresh, the FTJ-based memory enables non-destructive reading by utilizing the memory effect where the resistance state can be sensed without being altered. This eliminates the need for data rewriting operations while maintaining fast access speeds.
3Duration of action of stationary object
If data rewriting is performed, then data retention is maintained, but power consumption increases
Solution Approach 1:
The FTJ element with ferroelectric memory effect provides self-service by inherently maintaining data retention without requiring external refresh or rewrite operations. The non-volatile memory characteristic automatically preserves data state, eliminating the energy-consuming rewrite cycle needed in conventional DRAM and significantly reducing power consumption.
4Ease of manufacture
If conventional memory structures are used, then manufacturing is mature, but circuit area increases
Solution Approach 1:
The patent merges the FTJ element structure with the memory cell configuration, integrating the tunnel insulating film, ferroelectric dielectric layer, and electrode structures into a unified vertical stack. This merging enables high-density memory cells with reduced footprint while utilizing mature semiconductor manufacturing processes for depositing and patterning the multi-layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a semiconductor device that retains data without destructive reading, reduces power consumption, and minimizes circuit area, enhancing data retention and efficiency.
Implementation Method 1
The first FTJ element and the second FTJ element each include an input terminal, a tunnel insulating film, a dielectric, and an output terminal
Implementation Method 2
a dielectric having ferroelectricity
Data Source
AI summary
A semiconductor device that has lower power consumption and is capable of non-destructive reading is provided. The semiconductor device includes first to fourth transistors and first and second FTJ elements. The first FTJ element and the second FTJ element each include an input terminal, a tunnel insulating film, a dielectric, and an output terminal. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor, a gate of the fourth transistor, and the output terminal of the first FTJ element. One of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor, a gate of the third transistor, and the output terminal of the second FTJ element.