FTJ Memory Wafer Bonding After High-Temperature Ferroelectric Anneal

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Solution Overview

Problem

Existing ferroelectric memory devices face challenges in miniaturization and integration at the BEOL level due to low readout current and difficulty in forming a non-polarization layer, particularly when the ferroelectric film thickness is less than 5 nm, which affects the polarization property and device functionality.

Innovation Solution

A wafer-on-wafer process is employed to fabricate logic and ferroelectric memory devices separately, allowing thermal treatment of the ferroelectric film without damaging FEOL structures, enabling crystallization at temperatures between 400° C. and 1000° C. and improving device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the ferroelectric film thickness is reduced to less than 5 nm for miniaturization, then the device density and integration are improved, but the polarization property deteriorates and device functionality is lost

Engineering Contradiction:

Improveferroelectric film thicknessVSAvoidpolarization property

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent changes the crystalline structure parameter of the ferroelectric film from cubic to tetragonal phase, which maintains polarization properties even at ultrathin dimensions below 5 nm. This parameter change in crystal structure enables the film to retain ferroelectric functionality at reduced thickness for miniaturization

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite material system consisting of a tetragonal-phase ferroelectric film (such as Pb(Zr,X)O3 or Pb1-xLaxZr1-yTiyO3) integrated with electrode materials and interfacial layers. This composite structure enhances the polarization stability and prevents degradation at ultrathin dimensions

Inventive Principle:

Principle #40Composite materials

2Manufacturing precision

If thermal treatment is applied to crystallize the ferroelectric film, then the crystallization quality is improved, but the FEOL structures are damaged

Engineering Contradiction:

Improvecrystallization qualityVSAvoiddamage to FEOL structures

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent segments the fabrication process into two separate wafers: one for FEOL logic device fabrication and another for ferroelectric memory array fabrication. This segmentation allows independent thermal processing of each wafer, enabling high-temperature crystallization treatment of the ferroelectric film without exposing the temperature-sensitive FEOL structures to damaging conditions

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary bonding interface between the FEOL wafer and BEOL wafer. This bonding interface acts as a thermal barrier and mechanical connector, allowing the two wafers to be processed separately at different temperature regimes and then combined, protecting the FEOL structures from high-temperature damage while achieving good crystallization in the ferroelectric film

Inventive Principle:

Principle #24Intermediary (Mediator)

3Device complexity

If wafer-on-wafer bonding is performed to integrate logic and memory devices, then the device complexity is reduced and integration is improved, but the bonding precision and alignment are challenging

Engineering Contradiction:

Improveintegration structureVSAvoidbonding alignment

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary actions by forming alignment marks and bonding pads on both wafers before the actual bonding process. The alignment marks are pre-patterned with high precision, and the bonding pads are pre-formed with controlled dimensions and positions. This preliminary preparation enables accurate alignment during wafer-on-wafer bonding, reducing the challenges of bonding precision and alignment

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the crystallization quality of the ferroelectric film, improving the performance of ferroelectric memory devices while preventing damage to FEOL structures, thus overcoming thermal constraints and enabling efficient integration.

Implementation Method 1

performing a thermal treatment to the FTJ stacks in the second wafer

Methodology Applied

Scientific EffectThermal treatment: Heat Treatment

Implementation Method 2

enabling crystallization at temperatures between 400° C. and 1000° C. and improving device performance

Methodology Applied

Scientific EffectCrystallization: Crystallisation

Data Source

PatentUS20250364482A1Memory Device and Method of Forming The Same

Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method according to the present disclosure includes forming a plurality of transistors in a first wafer and forming a memory array in a second wafer. A first surface of the first wafer includes a first plurality of bonding pads electrically coupled to the transistors. The memory array includes a plurality of ferroelectric tunnel junction (FTJ) stacks. A second surface of the second wafer includes a second plurality of bonding pads electrically coupled to the FTJ stacks. The method also includes performing a thermal treatment to the FTJ stacks in the second wafer, and after the performing of the thermal treatment, bonding the first surface of the first wafer with the second surface of the second wafer. The transistors are coupled to the memory cells through the first plurality of bonding pads and the second plurality of bonding pads.