FTJ Memory Integration Using Post-Anneal Wafer Bonding
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Solution Overview
Problem
Existing ferroelectric memory devices face challenges in achieving crystallization of the ferroelectric layer without damaging FEOL structures, as high temperatures required for crystallization can deteriorate gate structures, and the formation of a non-polarization layer is difficult with thin ferroelectric films.
Innovation Solution
The wafer-on-wafer process is used to fabricate logic and ferroelectric memory devices separately, allowing for thermal treatment of the ferroelectric film up to 1000°C without affecting FEOL structures, thereby improving crystallization quality and preventing damage to logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperature thermal treatment is applied to crystallize the ferroelectric layer, then crystallization quality is improved, but FEOL structures are damaged
Solution Approach 1:
The patent divides the memory device fabrication into two separate wafers: a first wafer containing FEOL logic structures and a second wafer containing BEOL ferroelectric memory structures. This segmentation allows independent thermal processing of each wafer, enabling high-temperature treatment of the ferroelectric layer without exposing sensitive logic structures to damaging temperatures.
Solution Approach 2:
The ferroelectric layer is formed and thermally treated on the second wafer before bonding to the first wafer. The preliminary formation of the ferroelectric layer and its crystallization are completed on the second wafer, which can withstand high temperatures, before the wafers are bonded together. This preliminary action on the second wafer enables high-temperature processing without risking damage to the logic structures on the first wafer.
2Quantity of substance
If thin ferroelectric films are used to increase storage density, then device integration is improved, but formation of non-polarization layer becomes difficult
Solution Approach 1:
The patent introduces a dedicated second wafer as an intermediary substrate for forming and treating the thin ferroelectric layer. This second wafer serves as a specialized platform that can accommodate the specific manufacturing requirements of thin ferroelectric films, including high-temperature thermal treatment, before the completed memory structures are integrated with the logic structures on the first wafer.
Solution Approach 2:
The patent applies different quality requirements and processing conditions to different regions: the second wafer is specifically optimized for ferroelectric layer formation with local high-temperature capability, while the first wafer maintains logic structure compatibility. This local quality differentiation allows thin ferroelectric films to be manufactured with appropriate thermal treatment without compromising the overall device integration.
3Manufacturing precision
If wafer-on-wafer bonding is performed after thermal treatment, then crystallization quality is improved, but process complexity increases
Solution Approach 1:
The patent segments the fabrication process into two independent wafer processing lines that converge at the bonding stage. Each wafer can be processed independently with its own optimized process conditions, and the segmentation allows parallel processing that ultimately simplifies the overall manufacturing flow despite the additional bonding step.
Solution Approach 2:
The ferroelectric layer formation and crystallization are performed as preliminary actions on the second wafer before bonding. By completing these critical steps in advance on a dedicated wafer, the patent simplifies the final integration process and allows the bonding step to be performed under optimized conditions without the constraint of in-situ thermal treatment requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of ferroelectric memory devices by achieving better crystallization of the ferroelectric layer without risking damage to FEOL structures, enabling improved functionality and integration into BEOL structures.
Implementation Method 1
performing a thermal treatment to the FTJ stacks in the second wafer
Implementation Method 2
achieving better crystallization of the ferroelectric layer
Implementation Method 3
bonding the first surface of the first wafer with the second surface of the second wafer
Data Source
AI summary
A method according to the present disclosure includes forming a plurality of transistors in a first wafer and forming a memory array in a second wafer. A first surface of the first wafer includes a first plurality of bonding pads electrically coupled to the transistors. The memory array includes a plurality of ferroelectric tunnel junction (FTJ) stacks. A second surface of the second wafer includes a second plurality of bonding pads electrically coupled to the FTJ stacks. The method also includes performing a thermal treatment to the FTJ stacks in the second wafer, and after the performing of the thermal treatment, bonding the first surface of the first wafer with the second surface of the second wafer. The transistors are coupled to the memory cells through the first plurality of bonding pads and the second plurality of bonding pads.