Flash Translation Layer Address Mapping Space Reduction
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Solution Overview
Problem
The existing SSD firmware requires significant RAM resources for storing address mapping tables due to the large number of pages in flash memory, leading to increased costs and power consumption, as current methods necessitate loading all mapping tables into expensive and power-hungry DRAM.
Innovation Solution
A method that dynamically manages address mapping tables using cache space, where mappings are loaded only when needed, with cache hits allowing direct access and modified mappings written to NAND at designated times, reducing the need for full RAM loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all address mapping tables are loaded into DRAM to enable rapid search and update, then address mapping performance is improved, but RAM cost and power consumption increase
Solution Approach 1:
The patent divides the address mapping table into multiple segments or pages that can be independently loaded into DRAM. Instead of loading the entire mapping table, only the required segments are loaded into DRAM for rapid access, while other segments remain in slower memory. This segmentation allows the system to achieve fast address mapping performance for active data while using minimal DRAM resources.
Solution Approach 2:
The patent implements a dynamic memory management mechanism where the allocation of DRAM space for mapping tables is not fixed but adapts based on actual usage patterns. The system dynamically loads mapping table pages into DRAM when needed and evicts them when no longer required, optimizing the balance between performance and resource consumption based on real-time demands.
2Speed
If DRAM is used to store mapping tables for rapid access, then search and update speed is improved, but hardware cost increases
Solution Approach 1:
The patent applies partial action by loading only the necessary portion of the mapping table into DRAM rather than the complete table. The system identifies which mapping table pages are currently needed and loads only those into DRAM, leaving the rest in slower memory. This partial loading approach achieves sufficient search and update speed for active data while dramatically reducing DRAM capacity requirements.
3Productivity
If page mapping is used to achieve better randomness performance, then system performance is improved, but mapping table storage space increases
Solution Approach 1:
The patent segments the large mapping table required for page mapping into smaller manageable pages or blocks. Each segment can be independently managed and loaded into DRAM only when needed. This segmentation maintains the randomness performance benefits of page mapping while reducing the total storage space requirement by keeping only active segments in expensive DRAM memory.
Data Source
AI summary
A method of reducing FTL address mapping space, including: S1, obtaining a mpa and an offset according to a logical page address; S2, determining whether the mpa is hit in a cache; S3, determining whether a NAND is written into the mpa; S4, performing a nomap load operation, and returning an invalid mapping; S5, performing a map load operation; S6, directly searching a mpci representing a position of the mpa in the cache and searching a physical page address gppa with reference to the offset; S7, determining whether a mapping from a logical address to a physical address needs to be modified; S8, modifying a mapping table corresponding to the mpci in the cache, and marking a mp corresponding to the mpci as a dirty mp; S9, determining whether to trigger a condition of writing the mp into the NAND; and S10, writing the dirty mp into the NAND.