Flash Translation Layer Host-Controlled Recycle Ratio

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Solution Overview

Problem

The Flash Translation Layer (FTL) in solid state drives (SSDs) faces challenges in accurately determining the recycle ratio for flash memory block recycling due to unknown host write patterns, leading to increased latency, especially during bursts of data writes.

Innovation Solution

The FTL receives user recycle ratio information from the host device, allowing it to set a target recycle ratio that is more adaptive to the host's write conditions, thereby reducing latency by aligning recycling operations with anticipated write volumes and frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the FTL autonomously determines the recycle ratio based on internal estimates, then the FTL can independently manage memory block recycling, but the recycle operations do not accurately account for actual host write conditions resulting in long latency

Engineering Contradiction:
ImprovelatencyVSAvoidadaptability to host write conditions
Core Design Contradiction:
Loss of timeVSAdaptability or versatility

Solution Approach 1:

The host device provides feedback to the FTL about its write patterns and conditions. The FTL receives information from the host regarding upcoming write operations, and uses this feedback to dynamically adjust the recycle ratio and timing of recycle writes, thereby reducing latency while adapting to actual host write conditions.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The FTL performs preliminary actions by receiving advance information from the host about upcoming write operations. Based on this preliminary information, the FTL can proactively schedule recycle writes at optimal times before host writes occur, preventing latency issues rather than reacting to them after they occur.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If the FTL performs frequent recycle writes to ensure enough free blocks, then free space availability is improved, but host write latency increases due to interrupting host writes

Engineering Contradiction:
Improvefree memory blocksVSAvoidhost write latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The recycle ratio is made dynamic rather than fixed. The FTL adjusts the recycle ratio based on received host write conditions, allowing the system to flexibly balance between maintaining free blocks and minimizing host write latency. When host writes are light, the recycle ratio increases to free more blocks; when host writes are intense, the recycle ratio decreases to reduce latency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The FTL changes the recycle ratio parameter based on host write conditions. By receiving information about host write patterns and dynamically adjusting the recycle ratio parameter, the system optimizes the balance between maintaining sufficient free blocks and minimizing interruptions to host write operations, thereby reducing overall latency.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If the FTL performs less recycle writes to reduce latency, then host write latency is reduced, but free space availability decreases leading to potential write failures

Engineering Contradiction:
Improvehost write latencyVSAvoidfree memory blocks
Core Design Contradiction:
Loss of timeVSQuantity of substance

Solution Approach 1:

The host provides feedback to the FTL about its write patterns, enabling the FTL to accurately predict when host writes will occur. Based on this feedback, the FTL can perform recycle writes at optimal times when they will not conflict with host writes, thereby maintaining free space without increasing host write latency.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The FTL performs preliminary actions by scheduling recycle writes in advance based on received host write information. By knowing when host writes will occur, the FTL can proactively free up blocks before they are needed, ensuring sufficient free space is available without interrupting host write operations and thus avoiding increased latency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10564886B2Methods and apparatus for controlling flash translation layer recycle from host
Publication Date: 2020.02.18 SANDISK TECHNOLOGIES LLC
  • US10564886B2 patent drawing
  • US10564886B2 patent drawing
  • US10564886B2 patent drawing

AI summary

Aspects of the disclosure provide for control of a flash translation layer (FTL) in a non-volatile memory (NVM). Disclosed methods and apparatus provide for receiving a message in the FTL, which is transmitted from a host device, and includes desired recycle ratio information that is determined by the host where the ratio is a number of host writes to a number of recycle writes to be performed by the FTL. Based on the recycle ratio information, the FTL determines a target recycle ratio and performs recycling of memory blocks in the NVM based on the determined target recycle ratio. In this manner, the host device is able to exert control over the recycle ratio utilized in the FTL via a transmitted message, which allows the recycle ratio to be more adaptive to host write conditions known to the host device, but not known in the SSD.