FTL Write Path Segmentation for Higher Backend Command Throughput

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Solution Overview

Problem

The existing flash translation layer (FTL) architecture in memory sub-systems faces performance bottlenecks due to increased workload on the cursor module as the number of translation units (TUs) increases, leading to inefficient management of backend commands, which impacts throughput and makes asynchronous power loss and clean power down flows more difficult.

Innovation Solution

The FTL architecture decouples cursor operations from write command operations by introducing specialized streamer logic that processes write messages and generates backend commands, allowing for streamlined handling of different data paths and reducing redundant operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of translation units (TUs) is increased to handle more data, then the data processing capacity is improved, but the workload on the cursor module increases leading to performance bottlenecks

Engineering Contradiction:
Improvenumber of translation unitsVSAvoidcursor module throughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the cursor module into two separate specialized modules: a first cursor module dedicated to allocating data to block stripes and generating criteria sets, and a second cursor module dedicated to formatting TUs into backend commands. This segmentation allows each module to specialize in specific tasks, reducing the overall workload on any single cursor module and improving throughput as the number of TUs increases.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If the cursor module manages all backend command generation operations, then operational simplicity is maintained, but operational efficiency decreases due to redundant operations

Engineering Contradiction:
Improvecursor module structureVSAvoidbackend command generation efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the backend command generation process into two distinct operational phases handled by separate cursor modules: allocation (first cursor module) and formatting (second cursor module). This segmentation eliminates redundant operations by ensuring each module performs only its specialized function, thereby improving operational efficiency while maintaining manageable complexity through clear separation of duties.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a streamer logic component that acts as an intermediary between the two cursor modules and the memory device. The streamer logic receives criteria sets from the first cursor module and formatted commands from the second cursor module, coordinating their operations and enabling efficient data flow without requiring direct interaction between the specialized cursor modules.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If cursor operations and write command operations are combined in a single module, then system simplicity is maintained, but data integrity during power cycles is compromised

Engineering Contradiction:
ImproveFTL architectureVSAvoidcursor state persisting
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments cursor operations into two distinct modules with clearly defined boundaries and responsibilities. The first cursor module handles allocation and criteria set generation, while the second cursor module handles formatting. This segmentation improves data integrity during power cycles by ensuring that each module's state can be independently persisted and restored, reducing the risk of corruption that would occur in a monolithic design.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20260056661A1Flash translation layer write path architecture for increased throughput
Publication Date: 2026.02.26 MICRON TECHNOLOGY INC
  • US20260056661A1 patent drawing
  • US20260056661A1 patent drawing
  • US20260056661A1 patent drawing

AI summary

A processing device includes flash translation layer logic to be coupled to a memory device and that includes cursor logic to generate a criteria set associated with generating a backend command to be sent the memory device and streamer logic to access and employ the criteria set, e.g., aggregates translation units (TUs) received in one or more write messages. The criteria set enables accessing the plurality of TUs within a first format, of the one or more write messages, that depends on a data path associated with the one or more write messages. The streamer logic formats the aggregated TUs into the backend command having a second format for transmittal to the memory device. The backend command is to direct the memory device in writing TU data, associated with the TUs, to a memory array of the memory device.