FTP Memory Device with Selection Transistor for Power Reduction
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Solution Overview
Problem
Existing non-volatile memory devices face challenges with high power consumption, complex design, and limited data retention due to the need for high voltages and currents for programming and erasing, as well as unintended erasure of memory cells caused by electric stress during sector-level erasing in FTP memories.
Innovation Solution
Implementing both programming and erasing using the Fowler-Nordheim effect in a non-volatile memory device with a specific architecture that includes a selection transistor and a floating gate storage transistor, where the control gate is capacitively coupled with the floating gate, allowing for precise voltage application to prevent unwanted charge injection or extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high voltages and currents are used for programming and erasing memory cells, then programming speed is improved, but power consumption increases and data retention deteriorates due to electric stress on unselected cells
Solution Approach 1:
The memory device is divided into multiple independently controllable sectors, each with its own selection transistor. This allows programming and erasing operations to be performed on selected sectors only, isolating them from other sectors through the selection transistor control, thereby reducing power consumption and eliminating electric stress on unselected cells while maintaining high-speed operation on targeted cells
Solution Approach 2:
A selection transistor is introduced as an intermediary element between the control circuitry and the memory cells. This selection transistor acts as a gate that controls the application of high voltages and currents, allowing precise targeting of specific memory cells for programming/erasing operations while preventing these high-voltage effects from affecting adjacent or unselected cells, thus solving both power consumption and data retention issues
2Ease of manufacture
If sector-level erasing is implemented in FTP memories, then manufacturing complexity is reduced, but data retention deteriorates due to unintended erasure of memory cells caused by electric stress propagation
Solution Approach 1:
The memory array is segmented into multiple sectors with individual selection transistors for each cell. During erasing operations, only the selected sector is affected because the selection transistor isolates other sectors. This maintains the simplicity of sector-level erasing manufacturing while preventing electric stress propagation to unselected cells, thereby preserving data retention
Solution Approach 2:
The selection transistor provides local control over voltage and current application to specific memory cells or sectors. By controlling the selection transistor state, high-voltage erasing signals are confined to the intended sector only, creating a localized effect that prevents unwanted interference with adjacent sectors and maintains both manufacturing simplicity and data integrity
3Productivity
If multiple memory cells are programmed in parallel, then productivity is improved, but programming precision deteriorates due to current sharing and control difficulties
Solution Approach 1:
Each memory cell or sector is equipped with its own selection transistor, creating independent controllable units. This segmentation allows multiple cells to be programmed in parallel while maintaining precise control over each individual cell's programming process, as each selection transistor can be independently controlled to ensure proper current flow and programming conditions for its associated cell
Solution Approach 2:
The selection transistor serves multiple functions: it enables parallel operation by providing independent control paths for multiple cells, maintains programming precision through selective activation, and reduces power consumption by activating only necessary cells. This multi-functional element resolves the trade-off between parallelism and precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, simplifies charge pump design, enhances programming parallelism, and increases data retention by minimizing electric stress on unselected memory cells, enabling a higher number of programming and erasing operations without data loss.
Implementation Method 1
a control gate of the storage transistor formed in the second well; the control gate is capacitively coupled with the floating gate
Implementation Method 2
Implementing both programming and erasing using the Fowler-Nordheim effect in a non-volatile memory device
Data Source
AI summary
A non-volatile memory device integrated in a chip of semiconductor material. An embodiment of a memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of a first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, and a third region of the second type of conductivity that are formed in the first well; these regions define a selection transistor of MOS type and a storage transistor of floating gate MOS type that are coupled in series. Moreover, the memory device includes a selection gate of the selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well; the control gate is capacitively coupled with the floating gate.