Firmware TPM Seed Morphing for Secure Boot Attestation
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Solution Overview
Problem
Conventional Trusted Platform Modules (TPM) chips face challenges such as high costs, energy inefficiency, compatibility issues with certain devices, susceptibility to physical attacks, and lack of upgradability, which limit their widespread adoption in computing devices like mobile phones and tablets.
Innovation Solution
Implementing a firmware-based TPM (fTPM) with seed morphing techniques that load and execute boot chain components prior to the system integrated TPM, using encryption and identity seeds to establish trust and generate secure keys, allowing for secure attestation and key management without the need for a discrete TPM chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a discrete TPM chip is integrated into the motherboard, then security functionality is provided, but the bill of materials cost increases by about $1 to $2 per system
Solution Approach 1:
The patent combines the TPM security functionality with the system's existing secure elements or trusted execution environments, eliminating the need for a separate discrete TPM chip. This integration approach maintains security functionality while reducing bill of materials costs by consolidating components.
Solution Approach 2:
The patent implements a multi-functional security architecture where existing hardware components (such as secure boot processors, trusted execution environments, or hardware security modules) perform both their original functions and TPM security functions. This universal approach provides security functionality without adding dedicated TPM hardware.
2Reliability
If a discrete TPM chip is used, then platform authentication is enabled, but energy efficiency is reduced and power budget is impacted
Solution Approach 1:
The patent merges TPM authentication functions with existing low-power security processors or trusted execution environments that are already part of the system's power architecture. This integration allows platform authentication to occur within the existing power budget without adding the energy consumption of a separate TPM chip.
Solution Approach 2:
The patent enables the system's existing security infrastructure to perform authentication functions that would otherwise require a dedicated TPM chip. By utilizing already-powered security components for dual purposes, the system achieves platform authentication without additional energy expenditure.
3Reliability
If a discrete TPM chip is implemented, then security processing is provided, but the processor speed is reduced due to use of slow processors to meet BOM constraints
Solution Approach 1:
The patent integrates security processing functions into the system's existing high-performance processors or dedicated security accelerators, eliminating the need for separate slow TPM processors. This approach maintains both security processing capability and high processor speed by utilizing existing fast processing resources.
Solution Approach 2:
The patent extracts the security processing functions from the discrete TPM chip and relocates them to the system's existing high-speed processors or dedicated security processing units. This extraction allows security processing to occur at the speed of the host system's processors rather than being limited by slow TPM processors.
4Reliability
If a discrete TPM chip is used, then remote attestation is enabled, but compatibility with certain form factors is reduced
Solution Approach 1:
The patent implements a universal security architecture where existing hardware components provide both their primary functions and TPM security functions including remote attestation. This multi-functional approach enables remote attestation capability across diverse form factors without requiring form-factor-specific TPM chip implementations.
Solution Approach 2:
The patent combines remote attestation functionality with existing system components such as secure boot processors or trusted execution environments, eliminating the need for discrete TPM chips that would require specific form factor support. This integration provides form factor-agnostic security functionality.
5Reliability
If a discrete TPM chip is integrated, then security keys are generated, but vulnerability to physical attacks increases
Solution Approach 1:
The patent merges key generation and storage functions with existing secure hardware elements that are already protected against physical attacks, such as secure enclaves, hardware security modules, or protected memory regions. This integration maintains security key generation capability while leveraging the existing physical security protections of the host system.
Solution Approach 2:
The patent implements preliminary security measures by utilizing hardware components that are designed with inherent physical attack resistance, such as secure boot chains, hardware-enforced memory protection, and trusted execution environments. These pre-existing protections counter physical attack vectors before they can compromise key generation.
6Reliability
If a discrete TPM chip is deployed, then TPM functionality is provided, but upgradability is prevented
Solution Approach 1:
The patent implements a software-based or virtualized security architecture where TPM functionality is provided through firmware or software layers rather than hardwired hardware. This approach allows TPM functionality to be updated, upgraded, or modified through software updates without requiring hardware changes, enabling continuous improvement of security capabilities.
Solution Approach 2:
The patent employs dynamic security functionality through virtualized TPM implementations or firmware-based security modules that can be updated, reconfigured, or upgraded remotely. This dynamic approach contrasts with static discrete TPM chips, allowing the security functionality to adapt to new threats and requirements over time.
Data Source
AI summary
Computing devices that perform hardware rooted attestation are described, as are methods for use therewith, wherein such devices include a system integrated TPM (e.g., a firmware-based TPM), with m boot chain components loaded and executed prior to the system integrated TPM. Between powering-up of a device and the system integrated TPM being loaded and executed, seed morphing is performed for n=0 to m. This involves an nth encryption seed (ESn) being morphed into an n+1th encryption seed (ESn+1), under control of an nth boot chain component, by extending the nth encryption seed (ESn) with a measurement of the n+1th boot chain component to thereby generate the n+1th encryption seed (ESn+1). In a similar manner, an nth identity seed (ISn) is morphed into an n+1th identity seed (ISn+1). Such techniques establish trust in the system integrated TPM despite it not being the first component loaded and executed after powering-up.