Reconfigurable Full-Adder Logic Circuit for Compact FPGA Cryptography
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Solution Overview
Problem
Current reconfigurable logic circuits for cryptography in FPGAs face limitations in terms of area requirements and throughput, and require complex assembly code for implementation, which restricts their performance and flexibility.
Innovation Solution
A reconfigurable logic circuit with a full-adder-based cell structure that uses switching circuits and configuration bits to implement basic arithmetic functions, allowing for efficient mapping of cryptographic algorithms and providing side-channel protection through threshold implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If lookup tables are used for combinatorial functions in FPGAs, then reconfigurability is achieved, but area requirements and combinatorial delay increase
Solution Approach 1:
The lookup table is segmented into multiple smaller lookup tables, each handling a portion of the truth table. This segmentation reduces the area required for each individual LUT while maintaining the overall reconfigurability of the system through coordinated operation of multiple smaller units.
Solution Approach 2:
The patent introduces a new dimension to the LUT structure by adding a select input that controls which portion of the truth table is active. This dimensional extension allows the same physical hardware to implement multiple different logic functions by selectively activating different segments, thereby reducing area requirements while preserving reconfigurability.
2Adaptability or versatility
If lookup tables are used for combinatorial functions in FPGAs, then reconfigurability is achieved, but combinatorial delay increases
Solution Approach 1:
By segmenting the lookup table into smaller units, the combinatorial delay is reduced because each segment processes fewer inputs and can be implemented with fewer logic levels. The overall function is achieved by combining results from multiple segments, reducing the critical path delay while maintaining full reconfigurability.
Solution Approach 2:
The added select dimension enables faster switching between different logic functions by controlling which segment is active, reducing the time required to reconfigure the logic function compared to traditional LUT approaches that require complete table reprogramming.
3Adaptability or versatility
If complex assembly code is used for cryptographic algorithms, then functionality is achieved, but device complexity and configuration bits increase
Solution Approach 1:
The segmented LUT structure with select inputs provides a universal framework that can implement multiple cryptographic algorithms and functions using the same hardware resources. This multi-functionality reduces the number of configuration bits required compared to dedicated circuits for each cryptographic function, as the same segmented LUT can be reconfigured for different algorithms.
4Adaptability or versatility
If FPGAs are used for cryptographic applications, then flexibility and reconfigurability are achieved, but area requirements increase compared to dedicated hardware
Solution Approach 1:
The segmented LUT architecture allows cryptographic functions to be implemented using smaller, more area-efficient units compared to traditional large LUTs. By dividing the truth table into segments, the patent reduces the area required per LUT while maintaining the ability to implement complex cryptographic algorithms through coordinated operation of multiple segments.
Data Source
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AI summary
The present invention relates to a reconfigurable logic circuit comprising - a first, second and third switching circuit arranged for receiving a first input bit, a second input bit and a third input bit, respectively, and each arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, - a first exclusive OR logic block operable on the outputs of said first, second and third switching circuit and arranged to output a sum bit, - a fourth, fifth and sixth switching circuit arranged for receiving a fourth input bit, a fifth input bit and a sixth input bit and arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, - a first, second and third AND logic block, each arranged for receiving a different pair of the outputs of said fourth, fifth and sixth switching circuit, - a second exclusive OR logic block operable on the outputs of said first, second and third AND logic block and arranged to produce a carry output bit.